]> Pileus Git - ~andy/linux/commitdiff
drm/i915: Show render P state thresholds in sysfs
authorBen Widawsky <ben@bwidawsk.net>
Sat, 8 Sep 2012 02:43:44 +0000 (19:43 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 20 Sep 2012 12:23:06 +0000 (14:23 +0200)
This is useful for userspace utilities which wish to use the previous
interface, specifically for micromanaging the increase/decrease steps by
setting min == max.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_sysfs.c

index 1ffb9880d64ca6d81ea3f4d30a15353008b856cc..a2535151939704856f3bc0193f4d7e3b1819a918 100644 (file)
@@ -338,10 +338,46 @@ static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
 static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
 static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
 
+
+static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
+static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
+static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
+static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
+
+/* For now we have a static number of RP states */
+static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+       struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
+       struct drm_device *dev = minor->dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       u32 val, rp_state_cap;
+       ssize_t ret;
+
+       ret = mutex_lock_interruptible(&dev->struct_mutex);
+       if (ret)
+               return ret;
+       rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
+       mutex_unlock(&dev->struct_mutex);
+
+       if (attr == &dev_attr_gt_RP0_freq_mhz) {
+               val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
+       } else if (attr == &dev_attr_gt_RP1_freq_mhz) {
+               val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
+       } else if (attr == &dev_attr_gt_RPn_freq_mhz) {
+               val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
+       } else {
+               BUG();
+       }
+       return snprintf(buf, PAGE_SIZE, "%d", val);
+}
+
 static const struct attribute *gen6_attrs[] = {
        &dev_attr_gt_cur_freq_mhz.attr,
        &dev_attr_gt_max_freq_mhz.attr,
        &dev_attr_gt_min_freq_mhz.attr,
+       &dev_attr_gt_RP0_freq_mhz.attr,
+       &dev_attr_gt_RP1_freq_mhz.attr,
+       &dev_attr_gt_RPn_freq_mhz.attr,
        NULL,
 };