]> Pileus Git - ~andy/linux/commitdiff
ARM: dts: add pinctrl property for spi node for atmel SoC
authorWenyou Yang <wenyou.yang@atmel.com>
Wed, 3 Apr 2013 06:03:52 +0000 (14:03 +0800)
committerMark Brown <broonie@opensource.wolfsonmicro.com>
Wed, 24 Apr 2013 10:02:57 +0000 (11:02 +0100)
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
arch/arm/boot/dts/at91sam9260.dtsi
arch/arm/boot/dts/at91sam9263.dtsi
arch/arm/boot/dts/at91sam9g45.dtsi
arch/arm/boot/dts/at91sam9n12.dtsi
arch/arm/boot/dts/at91sam9x5.dtsi

index 6e31dc8f6f12de8979ab3a01536274e22c453160..39253b9aedd1279111a93e2e2c757342bf1ac72d 100644 (file)
                                        };
                                };
 
+                               spi0 {
+                                       pinctrl_spi0: spi0-0 {
+                                               atmel,pins =
+                                                       <0 0 0x1 0x0    /* PA0 periph A SPI0_MISO pin */
+                                                        0 1 0x1 0x0    /* PA1 periph A SPI0_MOSI pin */
+                                                        0 2 0x1 0x0>;  /* PA2 periph A SPI0_SPCK pin */
+                                       };
+                               };
+
+                               spi1 {
+                                       pinctrl_spi1: spi1-0 {
+                                               atmel,pins =
+                                                       <1 0 0x1 0x0    /* PB0 periph A SPI1_MISO pin */
+                                                        1 1 0x1 0x0    /* PB1 periph A SPI1_MOSI pin */
+                                                        1 2 0x1 0x0>;  /* PB2 periph A SPI1_SPCK pin */
+                                       };
+                               };
+
                                pioA: gpio@fffff400 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff400 0x200>;
                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xfffc8000 0x200>;
                                interrupts = <12 4 3>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_spi0>;
                                status = "disabled";
                        };
 
                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xfffcc000 0x200>;
                                interrupts = <13 4 3>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_spi1>;
                                status = "disabled";
                        };
 
index 6c6d9ae1577caddcaf199fb04172dac73fc183cf..94b58ab2cc08be9c841ff1cdd3e4553ca8ec40a4 100644 (file)
                                        };
                                };
 
+                               spi0 {
+                                       pinctrl_spi0: spi0-0 {
+                                               atmel,pins =
+                                                       <0 0 0x2 0x0    /* PA0 periph B SPI0_MISO pin */
+                                                        0 1 0x2 0x0    /* PA1 periph B SPI0_MOSI pin */
+                                                        0 2 0x2 0x0>;  /* PA2 periph B SPI0_SPCK pin */
+                                       };
+                               };
+
+                               spi1 {
+                                       pinctrl_spi1: spi1-0 {
+                                               atmel,pins =
+                                                       <1 12 0x1 0x0   /* PB12 periph A SPI1_MISO pin */
+                                                        1 13 0x1 0x0   /* PB13 periph A SPI1_MOSI pin */
+                                                        1 14 0x1 0x0>; /* PB14 periph A SPI1_SPCK pin */
+                                       };
+                               };
+
                                pioA: gpio@fffff200 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff200 0x200>;
                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xfffa4000 0x200>;
                                interrupts = <14 4 3>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_spi0>;
                                status = "disabled";
                        };
 
                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xfffa8000 0x200>;
                                interrupts = <15 4 3>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_spi1>;
                                status = "disabled";
                        };
                };
index e085b8af9a52df3adf5bed22c8786a40c35adc21..cfdf429578b59dfc39e28a5f71309a9d59f3ef41 100644 (file)
                                        };
                                };
 
+                               spi0 {
+                                       pinctrl_spi0: spi0-0 {
+                                               atmel,pins =
+                                                       <1 0 0x1 0x0    /* PB0 periph A SPI0_MISO pin */
+                                                        1 1 0x1 0x0    /* PB1 periph A SPI0_MOSI pin */
+                                                        1 2 0x1 0x0>;  /* PB2 periph A SPI0_SPCK pin */
+                                       };
+                               };
+
+                               spi1 {
+                                       pinctrl_spi1: spi1-0 {
+                                               atmel,pins =
+                                                       <1 14 0x1 0x0   /* PB14 periph A SPI1_MISO pin */
+                                                        1 15 0x1 0x0   /* PB15 periph A SPI1_MOSI pin */
+                                                        1 16 0x1 0x0>; /* PB16 periph A SPI1_SPCK pin */
+                                       };
+                               };
+
                                pioA: gpio@fffff200 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff200 0x200>;
                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xfffa4000 0x200>;
                                interrupts = <14 4 3>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_spi0>;
                                status = "disabled";
                        };
 
                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xfffa8000 0x200>;
                                interrupts = <15 4 3>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_spi1>;
                                status = "disabled";
                        };
                };
index f3f87ef30558bf970f7bffff62bc97536449ee33..b2961f1ea51b4063d7b4d3ac053586b586dfeed4 100644 (file)
                                        };
                                };
 
+                               spi0 {
+                                       pinctrl_spi0: spi0-0 {
+                                               atmel,pins =
+                                                       <0 11 0x1 0x0   /* PA11 periph A SPI0_MISO pin */
+                                                        0 12 0x1 0x0   /* PA12 periph A SPI0_MOSI pin */
+                                                        0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */
+                                       };
+                               };
+
+                               spi1 {
+                                       pinctrl_spi1: spi1-0 {
+                                               atmel,pins =
+                                                       <0 21 0x2 0x0   /* PA21 periph B SPI1_MISO pin */
+                                                        0 22 0x2 0x0   /* PA22 periph B SPI1_MOSI pin */
+                                                        0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */
+                                       };
+                               };
+
                                pioA: gpio@fffff400 {
                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                        reg = <0xfffff400 0x200>;
                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xf0000000 0x100>;
                                interrupts = <13 4 3>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_spi0>;
                                status = "disabled";
                        };
 
                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xf0004000 0x100>;
                                interrupts = <14 4 3>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_spi1>;
                                status = "disabled";
                        };
                };
index 83a4889f629bc0c6b8961e1dad0d40f6e57e2268..04fbf9d5b7d4204212980a92fbd8ff4f13f12f02 100644 (file)
                                        };
                                };
 
+                               spi0 {
+                                       pinctrl_spi0: spi0-0 {
+                                               atmel,pins =
+                                                       <0 11 0x1 0x0   /* PA11 periph A SPI0_MISO pin */
+                                                        0 12 0x1 0x0   /* PA12 periph A SPI0_MOSI pin */
+                                                        0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */
+                                       };
+                               };
+
+                               spi1 {
+                                       pinctrl_spi1: spi1-0 {
+                                               atmel,pins =
+                                                       <0 21 0x2 0x0   /* PA21 periph B SPI1_MISO pin */
+                                                        0 22 0x2 0x0   /* PA22 periph B SPI1_MOSI pin */
+                                                        0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */
+                                       };
+                               };
+
                                pioA: gpio@fffff400 {
                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                        reg = <0xfffff400 0x200>;
                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xf0000000 0x100>;
                                interrupts = <13 4 3>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_spi0>;
                                status = "disabled";
                        };
 
                                compatible = "atmel,at91rm9200-spi";
                                reg = <0xf0004000 0x100>;
                                interrupts = <14 4 3>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_spi1>;
                                status = "disabled";
                        };
                };