ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names

Add support for lookup of sdhci-s3c controller clocks using generic names
for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
[kgene.kim@samsung.com: fixed trailing whitespace]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 7dee8694486a8cbaf02139f3b2192fae5e14e915..5d8d4831e244ac2f0a90b10af3d5e03dd9a7dca7 100644 (file)
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -1154,42 +1154,6 @@ static struct clksrc_clk clksrcs[] = {
                .sources = &clkset_mout_mfc,
                .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
                .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.0",
-                       .parent         = &clk_dout_mmc0.clk,
-                       .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                       .ctrlbit        = (1 << 0),
-               },
-               .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.1",
-                       .parent         = &clk_dout_mmc1.clk,
-                       .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                       .ctrlbit        = (1 << 4),
-               },
-               .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.2",
-                       .parent         = &clk_dout_mmc2.clk,
-                       .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                       .ctrlbit        = (1 << 8),
-               },
-               .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.3",
-                       .parent         = &clk_dout_mmc3.clk,
-                       .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                       .ctrlbit        = (1 << 12),
-               },
-               .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
        }, {
                .clk            = {
                        .name           = "sclk_dwmmc",
@@ -1249,6 +1213,50 @@ static struct clksrc_clk clk_sclk_uart3 = {
        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
 };
 
+static struct clksrc_clk clk_sclk_mmc0 = {
+       .clk            = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.0",
+               .parent         = &clk_dout_mmc0.clk,
+               .enable         = exynos4_clksrc_mask_fsys_ctrl,
+               .ctrlbit        = (1 << 0),
+       },
+       .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+       .clk            = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.1",
+               .parent         = &clk_dout_mmc1.clk,
+               .enable         = exynos4_clksrc_mask_fsys_ctrl,
+               .ctrlbit        = (1 << 4),
+       },
+       .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+       .clk            = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.2",
+               .parent         = &clk_dout_mmc2.clk,
+               .enable         = exynos4_clksrc_mask_fsys_ctrl,
+               .ctrlbit        = (1 << 8),
+       },
+       .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk clk_sclk_mmc3 = {
+       .clk            = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.3",
+               .parent         = &clk_dout_mmc3.clk,
+               .enable         = exynos4_clksrc_mask_fsys_ctrl,
+               .ctrlbit        = (1 << 12),
+       },
+       .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+};
+
 /* Clock initialization code */
 static struct clksrc_clk *sysclks[] = {
        &clk_mout_apll,
@@ -1293,6 +1301,10 @@ static struct clksrc_clk *clksrc_cdev[] = {
        &clk_sclk_uart1,
        &clk_sclk_uart2,
        &clk_sclk_uart3,
+       &clk_sclk_mmc0,
+       &clk_sclk_mmc1,
+       &clk_sclk_mmc2,
+       &clk_sclk_mmc3,
 };
 
 static struct clk_lookup exynos4_clk_lookup[] = {
@@ -1300,6 +1312,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
+       CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+       CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+       CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+       CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
 };

diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index afbbe8bc21d14dd7a93e5acd5d359c1175d04e26..59f54d1d7f8b1772624d871bd520f7a094ff4892 100644 (file)
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -90,39 +90,38 @@ static struct clksrc_clk hsmmc_div[] = {
        },
 };
 
-static struct clksrc_clk hsmmc_mux[] = {
-       [0] = {
-               .clk    = {
-                       .name   = "hsmmc-if",
-                       .devname        = "s3c-sdhci.0",
-                       .ctrlbit = (1 << 6),
-                       .enable = s3c2443_clkcon_enable_s,
-               },
-               .sources = &(struct clksrc_sources) {
-                       .nr_sources = 2,
-                       .sources = (struct clk *[]) {
-                               [0] = &hsmmc_div[0].clk,
-                               [1] = NULL, /* to fix */
-                       },
-               },
-               .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
+static struct clksrc_clk hsmmc_mux0 = {
+       .clk    = {
+               .name           = "hsmmc-if",
+               .devname        = "s3c-sdhci.0",
+               .ctrlbit        = (1 << 6),
+               .enable         = s3c2443_clkcon_enable_s,
        },
-       [1] = {
-               .clk    = {
-                       .name   = "hsmmc-if",
-                       .devname        = "s3c-sdhci.1",
-                       .ctrlbit = (1 << 12),
-                       .enable = s3c2443_clkcon_enable_s,
+       .sources        = &(struct clksrc_sources) {
+               .nr_sources     = 2,
+               .sources        = (struct clk * []) {
+                       [0]     = &hsmmc_div[0].clk,
+                       [1]     = NULL, /* to fix */
                },
-               .sources = &(struct clksrc_sources) {
-                       .nr_sources = 2,
-                       .sources = (struct clk *[]) {
-                               [0] = &hsmmc_div[1].clk,
-                               [1] = NULL, /* to fix */
-                       },
+       },
+       .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
+};
+
+static struct clksrc_clk hsmmc_mux1 = {
+       .clk    = {
+               .name           = "hsmmc-if",
+               .devname        = "s3c-sdhci.1",
+               .ctrlbit        = (1 << 12),
+               .enable         = s3c2443_clkcon_enable_s,
+       },
+       .sources        = &(struct clksrc_sources) {
+               .nr_sources     = 2,
+               .sources        = (struct clk * []) {
+                       [0]     = &hsmmc_div[1].clk,
+                       [1]     = NULL, /* to fix */
                },
-               .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
        },
+       .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
 };
 
 static struct clk hsmmc0_clk = {
@@ -144,8 +143,14 @@ static struct clksrc_clk *clksrcs[] __initdata = {
        &hsspi_mux,
        &hsmmc_div[0],
        &hsmmc_div[1],
-       &hsmmc_mux[0],
-       &hsmmc_mux[1],
+       &hsmmc_mux0,
+       &hsmmc_mux1,
+};
+
+static struct clk_lookup s3c2416_clk_lookup[] = {
+       CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
+       CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
+       CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
 };
 
 void __init s3c2416_init_clocks(int xtal)
@@ -167,6 +172,7 @@ void __init s3c2416_init_clocks(int xtal)
                s3c_register_clksrc(clksrcs[ptr], 1);
 
        s3c24xx_register_clock(&hsmmc0_clk);
+       clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
 
        s3c_pwmclk_init();
 

diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 2addd988141cd08ac86fbc03521e4ebbf3430ffe..415c5406b17cae2f1fd8602031e13e5e7075db21 100644 (file)
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -242,24 +242,6 @@ static struct clk init_clocks[] = {
                .parent         = &clk_h,
                .enable         = s3c64xx_hclk_ctrl,
                .ctrlbit        = S3C_CLKCON_HCLK_UHOST,
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.0",
-               .parent         = &clk_h,
-               .enable         = s3c64xx_hclk_ctrl,
-               .ctrlbit        = S3C_CLKCON_HCLK_HSMMC0,
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.1",
-               .parent         = &clk_h,
-               .enable         = s3c64xx_hclk_ctrl,
-               .ctrlbit        = S3C_CLKCON_HCLK_HSMMC1,
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.2",
-               .parent         = &clk_h,
-               .enable         = s3c64xx_hclk_ctrl,
-               .ctrlbit        = S3C_CLKCON_HCLK_HSMMC2,
        }, {
                .name           = "otg",
                .parent         = &clk_h,
@@ -310,6 +292,29 @@ static struct clk init_clocks[] = {
        }
 };
 
+static struct clk clk_hsmmc0 = {
+       .name           = "hsmmc",
+       .devname        = "s3c-sdhci.0",
+       .parent         = &clk_h,
+       .enable         = s3c64xx_hclk_ctrl,
+       .ctrlbit        = S3C_CLKCON_HCLK_HSMMC0,
+};
+
+static struct clk clk_hsmmc1 = {
+       .name           = "hsmmc",
+       .devname        = "s3c-sdhci.1",
+       .parent         = &clk_h,
+       .enable         = s3c64xx_hclk_ctrl,
+       .ctrlbit        = S3C_CLKCON_HCLK_HSMMC1,
+};
+
+static struct clk clk_hsmmc2 = {
+       .name           = "hsmmc",
+       .devname        = "s3c-sdhci.2",
+       .parent         = &clk_h,
+       .enable         = s3c64xx_hclk_ctrl,
+       .ctrlbit        = S3C_CLKCON_HCLK_HSMMC2,
+};
 
 static struct clk clk_fout_apll = {
        .name           = "fout_apll",
@@ -577,36 +582,6 @@ static struct clksrc_sources clkset_camif = {
 
 static struct clksrc_clk clksrcs[] = {
        {
-               .clk    = {
-                       .name           = "mmc_bus",
-                       .devname        = "s3c-sdhci.0",
-                       .ctrlbit        = S3C_CLKCON_SCLK_MMC0,
-                       .enable         = s3c64xx_sclk_ctrl,
-               },
-               .reg_src        = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2  },
-               .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4  },
-               .sources        = &clkset_spi_mmc,
-       }, {
-               .clk    = {
-                       .name           = "mmc_bus",
-                       .devname        = "s3c-sdhci.1",
-                       .ctrlbit        = S3C_CLKCON_SCLK_MMC1,
-                       .enable         = s3c64xx_sclk_ctrl,
-               },
-               .reg_src        = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2  },
-               .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4  },
-               .sources        = &clkset_spi_mmc,
-       }, {
-               .clk    = {
-                       .name           = "mmc_bus",
-                       .devname        = "s3c-sdhci.2",
-                       .ctrlbit        = S3C_CLKCON_SCLK_MMC2,
-                       .enable         = s3c64xx_sclk_ctrl,
-               },
-               .reg_src        = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2  },
-               .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4  },
-               .sources        = &clkset_spi_mmc,
-       }, {
                .clk    = {
                        .name           = "usb-bus-host",
                        .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
@@ -697,6 +672,42 @@ static struct clksrc_clk clk_sclk_uclk = {
        .sources        = &clkset_uart,
 };
 
+static struct clksrc_clk clk_sclk_mmc0 = {
+       .clk    = {
+               .name           = "mmc_bus",
+               .devname        = "s3c-sdhci.0",
+               .ctrlbit        = S3C_CLKCON_SCLK_MMC0,
+               .enable         = s3c64xx_sclk_ctrl,
+       },
+       .reg_src        = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2  },
+       .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4  },
+       .sources        = &clkset_spi_mmc,
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+       .clk    = {
+               .name           = "mmc_bus",
+               .devname        = "s3c-sdhci.1",
+               .ctrlbit        = S3C_CLKCON_SCLK_MMC1,
+               .enable         = s3c64xx_sclk_ctrl,
+       },
+       .reg_src        = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2  },
+       .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4  },
+       .sources        = &clkset_spi_mmc,
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+       .clk    = {
+               .name           = "mmc_bus",
+               .devname        = "s3c-sdhci.2",
+               .ctrlbit        = S3C_CLKCON_SCLK_MMC2,
+               .enable         = s3c64xx_sclk_ctrl,
+       },
+       .reg_src        = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2  },
+       .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4  },
+       .sources        = &clkset_spi_mmc,
+};
+
 /* Clock initialisation code */
 
 static struct clksrc_clk *init_parents[] = {
@@ -707,11 +718,26 @@ static struct clksrc_clk *init_parents[] = {
 
 static struct clksrc_clk *clksrc_cdev[] = {
        &clk_sclk_uclk,
+       &clk_sclk_mmc0,
+       &clk_sclk_mmc1,
+       &clk_sclk_mmc2,
+};
+
+static struct clk *clk_cdev[] = {
+       &clk_hsmmc0,
+       &clk_hsmmc1,
+       &clk_hsmmc2,
 };
 
 static struct clk_lookup s3c64xx_clk_lookup[] = {
        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
+       CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+       CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+       CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+       CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+       CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+       CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
 };
 
 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
@@ -834,6 +860,10 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
+       s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+       for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
+               s3c_disable_clocks(clk_cdev[cnt], 1);
+
        s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
        for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)

diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 9d644ece260461245572de030505e9c27473671e..69829ba9c01bd58797c9807a7f5f946888a7ff7b 100644 (file)
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -425,24 +425,6 @@ static struct clk init_clocks_off[] = {
                .parent         = &clk_div_d0_bus.clk,
                .enable         = s5pc100_d0_2_ctrl,
                .ctrlbit        = (1 << 1),
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.2",
-               .parent         = &clk_div_d1_bus.clk,
-               .enable         = s5pc100_d1_0_ctrl,
-               .ctrlbit        = (1 << 7),
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.1",
-               .parent         = &clk_div_d1_bus.clk,
-               .enable         = s5pc100_d1_0_ctrl,
-               .ctrlbit        = (1 << 6),
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.0",
-               .parent         = &clk_div_d1_bus.clk,
-               .enable         = s5pc100_d1_0_ctrl,
-               .ctrlbit        = (1 << 5),
        }, {
                .name           = "modemif",
                .parent         = &clk_div_d1_bus.clk,
@@ -711,6 +693,30 @@ static struct clk init_clocks_off[] = {
        },
 };
 
+static struct clk clk_hsmmc2 = {
+       .name           = "hsmmc",
+       .devname        = "s3c-sdhci.2",
+       .parent         = &clk_div_d1_bus.clk,
+       .enable         = s5pc100_d1_0_ctrl,
+       .ctrlbit        = (1 << 7),
+};
+
+static struct clk clk_hsmmc1 = {
+       .name           = "hsmmc",
+       .devname        = "s3c-sdhci.1",
+       .parent         = &clk_div_d1_bus.clk,
+       .enable         = s5pc100_d1_0_ctrl,
+       .ctrlbit        = (1 << 6),
+};
+
+static struct clk clk_hsmmc0 = {
+       .name           = "hsmmc",
+       .devname        = "s3c-sdhci.0",
+       .parent         = &clk_div_d1_bus.clk,
+       .enable         = s5pc100_d1_0_ctrl,
+       .ctrlbit        = (1 << 5),
+};
+
 static struct clk clk_vclk54m = {
        .name           = "vclk_54m",
        .rate           = 54000000,
@@ -1012,39 +1018,6 @@ static struct clksrc_clk clksrcs[] = {
                .sources = &clk_src_group7,
                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
-       }, {
-               .clk    = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.0",
-                       .ctrlbit        = (1 << 12),
-                       .enable         = s5pc100_sclk1_ctrl,
-
-               },
-               .sources = &clk_src_mmc0,
-               .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
-               .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
-       }, {
-               .clk    = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.1",
-                       .ctrlbit        = (1 << 13),
-                       .enable         = s5pc100_sclk1_ctrl,
-
-               },
-               .sources = &clk_src_mmc12,
-               .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
-               .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
-       }, {
-               .clk    = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.2",
-                       .ctrlbit        = (1 << 14),
-                       .enable         = s5pc100_sclk1_ctrl,
-
-               },
-               .sources = &clk_src_mmc12,
-               .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
-               .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
        }, {
                .clk    = {
                        .name           = "sclk_irda",
@@ -1099,6 +1072,42 @@ static struct clksrc_clk clk_sclk_uart = {
        .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
 };
 
+static struct clksrc_clk clk_sclk_mmc0 = {
+       .clk    = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.0",
+               .ctrlbit        = (1 << 12),
+               .enable         = s5pc100_sclk1_ctrl,
+       },
+       .sources = &clk_src_mmc0,
+       .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
+       .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+       .clk    = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.1",
+               .ctrlbit        = (1 << 13),
+               .enable         = s5pc100_sclk1_ctrl,
+       },
+       .sources = &clk_src_mmc12,
+       .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
+       .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+       .clk    = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.2",
+               .ctrlbit        = (1 << 14),
+               .enable         = s5pc100_sclk1_ctrl,
+       },
+       .sources = &clk_src_mmc12,
+       .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
+       .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
+};
+
 /* Clock initialisation code */
 static struct clksrc_clk *sysclks[] = {
        &clk_mout_apll,
@@ -1128,8 +1137,17 @@ static struct clksrc_clk *sysclks[] = {
        &clk_sclk_spdif,
 };
 
+static struct clk *clk_cdev[] = {
+       &clk_hsmmc0,
+       &clk_hsmmc1,
+       &clk_hsmmc2,
+};
+
 static struct clksrc_clk *clksrc_cdev[] = {
        &clk_sclk_uart,
+       &clk_sclk_mmc0,
+       &clk_sclk_mmc1,
+       &clk_sclk_mmc2,
 };
 
 void __init_or_cpufreq s5pc100_setup_clocks(void)
@@ -1274,6 +1292,12 @@ static struct clk *clks[] __initdata = {
 static struct clk_lookup s5pc100_clk_lookup[] = {
        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
+       CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+       CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+       CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+       CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+       CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+       CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
 };
 
 void __init s5pc100_register_clocks(void)
@@ -1294,6 +1318,10 @@ void __init s5pc100_register_clocks(void)
        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
        clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
 
+       s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+       for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+               s3c_disable_clocks(clk_cdev[ptr], 1);
+
        s3c24xx_register_clock(&dummy_apb_pclk);
 
        s3c_pwmclk_init();

diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 43a045d354ec4d33ca84ceae0b545fd35483e8b6..dc4586b2b32292d2767656869cbf4eecad2ab827 100644 (file)
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -398,30 +398,6 @@ static struct clk init_clocks_off[] = {
                .parent         = &clk_hclk_psys.clk,
                .enable         = s5pv210_clk_ip1_ctrl,
                .ctrlbit        = (1<<25),
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.0",
-               .parent         = &clk_hclk_psys.clk,
-               .enable         = s5pv210_clk_ip2_ctrl,
-               .ctrlbit        = (1<<16),
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.1",
-               .parent         = &clk_hclk_psys.clk,
-               .enable         = s5pv210_clk_ip2_ctrl,
-               .ctrlbit        = (1<<17),
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.2",
-               .parent         = &clk_hclk_psys.clk,
-               .enable         = s5pv210_clk_ip2_ctrl,
-               .ctrlbit        = (1<<18),
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.3",
-               .parent         = &clk_hclk_psys.clk,
-               .enable         = s5pv210_clk_ip2_ctrl,
-               .ctrlbit        = (1<<19),
        }, {
                .name           = "systimer",
                .parent         = &clk_pclk_psys.clk,
@@ -559,6 +535,38 @@ static struct clk init_clocks[] = {
        },
 };
 
+static struct clk clk_hsmmc0 = {
+       .name           = "hsmmc",
+       .devname        = "s3c-sdhci.0",
+       .parent         = &clk_hclk_psys.clk,
+       .enable         = s5pv210_clk_ip2_ctrl,
+       .ctrlbit        = (1<<16),
+};
+
+static struct clk clk_hsmmc1 = {
+       .name           = "hsmmc",
+       .devname        = "s3c-sdhci.1",
+       .parent         = &clk_hclk_psys.clk,
+       .enable         = s5pv210_clk_ip2_ctrl,
+       .ctrlbit        = (1<<17),
+};
+
+static struct clk clk_hsmmc2 = {
+       .name           = "hsmmc",
+       .devname        = "s3c-sdhci.2",
+       .parent         = &clk_hclk_psys.clk,
+       .enable         = s5pv210_clk_ip2_ctrl,
+       .ctrlbit        = (1<<18),
+};
+
+static struct clk clk_hsmmc3 = {
+       .name           = "hsmmc",
+       .devname        = "s3c-sdhci.3",
+       .parent         = &clk_hclk_psys.clk,
+       .enable         = s5pv210_clk_ip2_ctrl,
+       .ctrlbit        = (1<<19),
+};
+
 static struct clk *clkset_uart_list[] = {
        [6] = &clk_mout_mpll.clk,
        [7] = &clk_mout_epll.clk,
@@ -864,46 +872,6 @@ static struct clksrc_clk clksrcs[] = {
                .sources = &clkset_group2,
                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.0",
-                       .enable         = s5pv210_clk_mask0_ctrl,
-                       .ctrlbit        = (1 << 8),
-               },
-               .sources = &clkset_group2,
-               .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
-               .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.1",
-                       .enable         = s5pv210_clk_mask0_ctrl,
-                       .ctrlbit        = (1 << 9),
-               },
-               .sources = &clkset_group2,
-               .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
-               .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.2",
-                       .enable         = s5pv210_clk_mask0_ctrl,
-                       .ctrlbit        = (1 << 10),
-               },
-               .sources = &clkset_group2,
-               .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
-               .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.3",
-                       .enable         = s5pv210_clk_mask0_ctrl,
-                       .ctrlbit        = (1 << 11),
-               },
-               .sources = &clkset_group2,
-               .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
-               .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
        }, {
                .clk            = {
                        .name           = "sclk_mfc",
@@ -1030,11 +998,70 @@ static struct clksrc_clk clk_sclk_uart3  = {
        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
 };
 
+static struct clksrc_clk clk_sclk_mmc0 = {
+       .clk            = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.0",
+               .enable         = s5pv210_clk_mask0_ctrl,
+               .ctrlbit        = (1 << 8),
+       },
+       .sources = &clkset_group2,
+       .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
+       .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+       .clk            = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.1",
+               .enable         = s5pv210_clk_mask0_ctrl,
+               .ctrlbit        = (1 << 9),
+       },
+       .sources = &clkset_group2,
+       .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
+       .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+       .clk            = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.2",
+               .enable         = s5pv210_clk_mask0_ctrl,
+               .ctrlbit        = (1 << 10),
+       },
+       .sources = &clkset_group2,
+       .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
+       .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc3 = {
+       .clk            = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.3",
+               .enable         = s5pv210_clk_mask0_ctrl,
+               .ctrlbit        = (1 << 11),
+       },
+       .sources = &clkset_group2,
+       .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
+       .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
+};
+
 static struct clksrc_clk *clksrc_cdev[] = {
        &clk_sclk_uart0,
        &clk_sclk_uart1,
        &clk_sclk_uart2,
        &clk_sclk_uart3,
+       &clk_sclk_mmc0,
+       &clk_sclk_mmc1,
+       &clk_sclk_mmc2,
+       &clk_sclk_mmc3,
+};
+
+static struct clk *clk_cdev[] = {
+       &clk_hsmmc0,
+       &clk_hsmmc1,
+       &clk_hsmmc2,
+       &clk_hsmmc3,
 };
 
 /* Clock initialisation code */
@@ -1282,6 +1309,14 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
        CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
        CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
        CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
+       CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+       CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+       CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+       CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3),
+       CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+       CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+       CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+       CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
 };
 
 void __init s5pv210_register_clocks(void)
@@ -1306,6 +1341,10 @@ void __init s5pv210_register_clocks(void)
        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
        clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
 
+       s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+       for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+               s3c_disable_clocks(clk_cdev[ptr], 1);
+
        s3c24xx_register_clock(&dummy_apb_pclk);
        s3c_pwmclk_init();
 }

diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 4eab2cca2d927982aa264a7b5e1da7dff3b70b70..95e68190d59305bbe0d65787abd1f3c66cd151b7 100644 (file)
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -426,12 +426,6 @@ static struct clk init_clocks[] = {
                .parent         = &clk_h,
                .enable         = s3c2443_clkcon_enable_h,
                .ctrlbit        = S3C2443_HCLKCON_DMA5,
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.1",
-               .parent         = &clk_h,
-               .enable         = s3c2443_clkcon_enable_h,
-               .ctrlbit        = S3C2443_HCLKCON_HSMMC,
        }, {
                .name           = "gpio",
                .parent         = &clk_p,
@@ -514,6 +508,14 @@ static struct clk init_clocks[] = {
        }
 };
 
+static struct clk hsmmc1_clk = {
+       .name           = "hsmmc",
+       .devname        = "s3c-sdhci.1",
+       .parent         = &clk_h,
+       .enable         = s3c2443_clkcon_enable_h,
+       .ctrlbit        = S3C2443_HCLKCON_HSMMC,
+};
+
 static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
 {
        clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
@@ -579,6 +581,7 @@ static struct clk *clks[] __initdata = {
        &clk_epll,
        &clk_usb_bus,
        &clk_armdiv,
+       &hsmmc1_clk,
 };
 
 static struct clksrc_clk *clksrcs[] __initdata = {
@@ -595,6 +598,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
        CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
+       CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
 };
 
 void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,