ARM: virt: avoid clobbering lr when forcing svc mode

The safe_svcmode_maskall macro is used to ensure that we are running in
svc mode, causing an exception return from hvc mode if required.

This patch removes the unneeded lr clobber from the macro and operates
entirely on the temporary parameter register instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[will: updated comment]
Signed-off-by: Will Deacon <will.deacon@arm.com>

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index eb87200aa4b566645677523e0751f03bcbb06e0f..05ee9eebad6b3feb7da31a225f64d10b297d897b 100644 (file)
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -246,18 +246,14 @@
  *
  * This macro is intended for forcing the CPU into SVC mode at boot time.
  * you cannot return to the original mode.
- *
- * Beware, it also clobers LR.
  */
 .macro safe_svcmode_maskall reg:req
 #if __LINUX_ARM_ARCH__ >= 6
        mrs     \reg , cpsr
-       mov     lr , \reg
-       and     lr , lr , #MODE_MASK
-       cmp     lr , #HYP_MODE
-       orr     \reg , \reg , #PSR_I_BIT | PSR_F_BIT
+       eor     \reg, \reg, #HYP_MODE
+       tst     \reg, #MODE_MASK
        bic     \reg , \reg , #MODE_MASK
-       orr     \reg , \reg , #SVC_MODE
+       orr     \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
 THUMB( orr     \reg , \reg , #PSR_T_BIT        )
        bne     1f
        orr     \reg, \reg, #PSR_A_BIT