]> Pileus Git - ~andy/linux/commitdiff
powerpc/mpic: Add get_version API both for internal and external use
authorHongtao Jia <hongtao.jia@freescale.com>
Wed, 10 Apr 2013 02:52:55 +0000 (10:52 +0800)
committerScott Wood <scottwood@freescale.com>
Mon, 1 Jul 2013 23:38:28 +0000 (18:38 -0500)
MPIC version is useful information for both mpic_alloc() and mpic_init().
The patch provide an API to get MPIC version for reusing the code.
Also, some other IP block may need MPIC version for their own use.
The API for external use is also provided.

Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
arch/powerpc/include/asm/mpic.h
arch/powerpc/sysdev/mpic.c

index c0f9ef90f0b8407a22987dfe4c83c73ed0cbc1d3..ea6bf7220da99e02d4e88f9ceff8231aa342f7af 100644 (file)
@@ -393,6 +393,9 @@ struct mpic
 #define        MPIC_REGSET_STANDARD            MPIC_REGSET(0)  /* Original MPIC */
 #define        MPIC_REGSET_TSI108              MPIC_REGSET(1)  /* Tsi108/109 PIC */
 
+/* Get the version of primary MPIC */
+extern u32 fsl_mpic_primary_get_version(void);
+
 /* Allocate the controller structure and setup the linux irq descs
  * for the range if interrupts passed in. No HW initialization is
  * actually performed.
index 3cc2f9159ab1185f9f8f00ccefbcac14995ae6b1..1a4e19c6a688c5c7460d8475681e87ba248728da 100644 (file)
@@ -1173,10 +1173,33 @@ static struct irq_domain_ops mpic_host_ops = {
        .xlate = mpic_host_xlate,
 };
 
+static u32 fsl_mpic_get_version(struct mpic *mpic)
+{
+       u32 brr1;
+
+       if (!(mpic->flags & MPIC_FSL))
+               return 0;
+
+       brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
+                       MPIC_FSL_BRR1);
+
+       return brr1 & MPIC_FSL_BRR1_VER;
+}
+
 /*
  * Exported functions
  */
 
+u32 fsl_mpic_primary_get_version(void)
+{
+       struct mpic *mpic = mpic_primary;
+
+       if (mpic)
+               return fsl_mpic_get_version(mpic);
+
+       return 0;
+}
+
 struct mpic * __init mpic_alloc(struct device_node *node,
                                phys_addr_t phys_addr,
                                unsigned int flags,
@@ -1323,7 +1346,6 @@ struct mpic * __init mpic_alloc(struct device_node *node,
        mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
 
        if (mpic->flags & MPIC_FSL) {
-               u32 brr1;
                int ret;
 
                /*
@@ -1334,9 +1356,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
                mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
                         MPIC_CPU_THISBASE, 0x1000);
 
-               brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
-                               MPIC_FSL_BRR1);
-               fsl_version = brr1 & MPIC_FSL_BRR1_VER;
+               fsl_version = fsl_mpic_get_version(mpic);
 
                /* Error interrupt mask register (EIMR) is required for
                 * handling individual device error interrupts. EIMR
@@ -1526,9 +1546,7 @@ void __init mpic_init(struct mpic *mpic)
        mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
 
        if (mpic->flags & MPIC_FSL) {
-               u32 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
-                                     MPIC_FSL_BRR1);
-               u32 version = brr1 & MPIC_FSL_BRR1_VER;
+               u32 version = fsl_mpic_get_version(mpic);
 
                /*
                 * Timer group B is present at the latest in MPIC 3.1 (e.g.