Merge branch 'imx/cpuidle' into next/pm

* imx/cpuidle:
  ARM: imx: Add imx6q cpuidle driver
  ARM: imx: Add imx5 cpuidle
  ARM: imx: Add common imx cpuidle init functionality.
  ARM: imx: Enable imx53 low power idle
  ARM: imx: clean and consolidate imx5 suspend and idle code
  ARM: imx: Add comments to tzic_enable_waker()
  ARM: imx: Modify IMX_IO_P2V macro

Resolved trivial context conflict in arch/arm/plat-mxc/include/mach/common.h

Signed-off-by: Olof Johansson <olof@lixom.net>

diff --combined arch/arm/mach-imx/clk-imx51-imx53.c
index a2200c77bf70dcdc09c44d642fe09656f36f0fcb,8a2e7194b221d04c684e90f6c0affab1199672a1..4b89fae14a5a272d6c32b0ed34e2d598bae686e2
--- 1/arch/arm/mach-imx/clk-imx51-imx53.c
--- 2/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@@ -104,12 -104,12 +104,12 @@@ static void __init mx5_clocks_common_in
                                periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
        clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
                                main_bus_sel, ARRAY_SIZE(main_bus_sel));
 -      clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCDR, 1, 1,
 +      clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
                                per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
        clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
        clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
        clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
 -      clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCDR, 1, 0,
 +      clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
                                per_root_sel, ARRAY_SIZE(per_root_sel));
        clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
        clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
@@@ -172,7 -172,7 +172,7 @@@
        clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "ipg", MXC_CCM_CCGR2, 12);
        clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
        clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "ipg", MXC_CCM_CCGR2, 16);
 -      clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", MXC_CCM_CCGR2, 18);
 +      clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per_root", MXC_CCM_CCGR2, 18);
        clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
        clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
        clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
@@@ -279,6 -279,7 +279,7 @@@
        clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
        clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0");
        clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
+       clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
  
        /* Set SDHC parents to be PLL2 */
        clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
@@@ -336,7 -337,6 +337,6 @@@ int __init mx51_clocks_init(unsigned lo
        clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
        clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
        clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
-       clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
        clk_register_clkdev(clk[ipu_gate], "bus", "imx51-ipu");
        clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu");
        clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu");
@@@ -366,7 -366,8 +366,7 @@@
        clk_set_rate(clk[esdhc_b_podf], 166250000);
  
        /* System timer */
 -      mxc_timer_init(NULL, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
 -              MX51_INT_GPT);
 +      mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
  
        clk_prepare_enable(clk[iim_gate]);
        imx_print_silicon_rev("i.MX51", mx51_revision());
@@@ -451,7 -452,8 +451,7 @@@ int __init mx53_clocks_init(unsigned lo
        clk_set_rate(clk[esdhc_b_podf], 200000000);
  
        /* System timer */
 -      mxc_timer_init(NULL, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
 -              MX53_INT_GPT);
 +      mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT);
  
        clk_prepare_enable(clk[iim_gate]);
        imx_print_silicon_rev("i.MX53", mx53_revision());

diff --combined arch/arm/mach-imx/mm-imx5.c
index 1d003053d5621bd45341030b9f58db08f78990ac,cc7e7ca52908f3334cf41be48379494a7fd6e861..f19d604e1b2aea6e89ab7c86fc6c6917e57ce48a
--- 1/arch/arm/mach-imx/mm-imx5.c
--- 2/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@@ -16,7 -16,6 +16,6 @@@
  #include <linux/clk.h>
  #include <linux/pinctrl/machine.h>
  
- #include <asm/system_misc.h>
  #include <asm/mach/map.h>
  
  #include <mach/hardware.h>
@@@ -24,24 -23,6 +23,6 @@@
  #include <mach/devices-common.h>
  #include <mach/iomux-v3.h>
  
- static struct clk *gpc_dvfs_clk;
- 
- static void imx5_idle(void)
- {
-       /* gpc clock is needed for SRPG */
-       if (gpc_dvfs_clk == NULL) {
-               gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
-               if (IS_ERR(gpc_dvfs_clk))
-                       return;
-               clk_prepare(gpc_dvfs_clk);
-       }
-       clk_enable(gpc_dvfs_clk);
-       mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
-       if (!tzic_enable_wake())
-               cpu_do_idle();
-       clk_disable(gpc_dvfs_clk);
- }
- 
  /*
   * Define the MX50 memory map.
   */
@@@ -105,7 -86,6 +86,6 @@@ void __init imx51_init_early(void
        mxc_set_cpu_type(MXC_CPU_MX51);
        mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
        mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
-       arm_pm_idle = imx5_idle;
  }
  
  void __init imx53_init_early(void)
@@@ -202,8 -182,6 +182,8 @@@ void __init imx51_soc_init(void
        mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
        mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
  
 +      pinctrl_provide_dummies();
 +
        /* i.mx51 has the i.mx35 type sdma */
        imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
  
@@@ -243,4 -221,10 +223,10 @@@ void __init imx53_soc_init(void
  void __init imx51_init_late(void)
  {
        mx51_neon_fixup();
+       imx51_pm_init();
+ }
+ 
+ void __init imx53_init_late(void)
+ {
+       imx53_pm_init();
  }

diff --combined arch/arm/plat-mxc/include/mach/common.h
index e429ca1b814a179522bdf2bc9bb9e514ac136efc,3314e69525568b11c412f000b0fc7f2b9e684d24..7ca15044154f29c7a5a5c5ac12220d0a3103b548
--- 1/arch/arm/plat-mxc/include/mach/common.h
--- 2/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@@ -54,8 -54,9 +54,9 @@@ extern void imx50_soc_init(void)
  extern void imx51_soc_init(void);
  extern void imx53_soc_init(void);
  extern void imx51_init_late(void);
 -extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
 -extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
+ extern void imx53_init_late(void);
 +extern void epit_timer_init(void __iomem *base, int irq);
 +extern void mxc_timer_init(void __iomem *, int);
  extern int mx1_clocks_init(unsigned long fref);
  extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
  extern int mx25_clocks_init(void);
@@@ -95,7 -96,6 +96,6 @@@ enum mx3_cpu_pwr_mode 
  };
  
  extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
- extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
  extern void imx_print_silicon_rev(const char *cpu, int srev);
  
  void avic_handle_irq(struct pt_regs *);
@@@ -146,8 -146,12 +146,12 @@@ extern void imx6q_clock_map_io(void)
  
  #ifdef CONFIG_PM
  extern void imx6q_pm_init(void);
+ extern void imx51_pm_init(void);
+ extern void imx53_pm_init(void);
  #else
  static inline void imx6q_pm_init(void) {}
+ static inline void imx51_pm_init(void) {}
+ static inline void imx53_pm_init(void) {}
  #endif
  
  #ifdef CONFIG_NEON