]> Pileus Git - ~andy/linux/commitdiff
drm/i915: Always flush tiling changes before accessing through the GTT
authorChris Wilson <chris@chris-wilson.co.uk>
Sat, 14 Apr 2012 08:55:51 +0000 (09:55 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 18 Apr 2012 08:48:38 +0000 (10:48 +0200)
As we defer updating the fence register from set-tiling to the point of
use, we need to declare every access through the GTT as either fenced or
unfenced.

This patches fixes an old bug in the execbuffer relocation processing
which could conceivably be hit by a pathological userspace.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_gem_execbuffer.c

index 2a24d0cd9b4641493c13ec30f6921a53dba6cce7..1a0d54f278c4c62da4f2d34991a70c130b4eb112 100644 (file)
@@ -381,7 +381,11 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
                uint32_t __iomem *reloc_entry;
                void __iomem *reloc_page;
 
-               ret = i915_gem_object_set_to_gtt_domain(obj, 1);
+               ret = i915_gem_object_set_to_gtt_domain(obj, true);
+               if (ret)
+                       return ret;
+
+               ret = i915_gem_object_put_fence(obj);
                if (ret)
                        return ret;