Merge branch 'clk-tegra-next' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux...

diff --git a/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt
index 5757f9abfc26e10ac737ff1278aaa885721c9abc..1bae8527eb9bc15cdb148daa861ee79272098094 100644 (file)
--- a/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt
+++ b/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt
@@ -19,6 +19,6 @@ Example:
                compatible = "fixed-factor-clock";
                clocks = <&parentclk>;
                #clock-cells = <0>;
-               div = <2>;
-               mult = <1>;
+               clock-div = <2>;
+               clock-mult = <1>;
        };

diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index a33f46f20a415c7fb925f1531a6791c4ecd2055c..753d0b78476226310fde948e181e675188cbff45 100644 (file)
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -55,6 +55,30 @@ static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
        return rate_ops->recalc_rate(rate_hw, parent_rate);
 }
 
+static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
+                                       unsigned long *best_parent_rate,
+                                       struct clk **best_parent_p)
+{
+       struct clk_composite *composite = to_clk_composite(hw);
+       const struct clk_ops *rate_ops = composite->rate_ops;
+       const struct clk_ops *mux_ops = composite->mux_ops;
+       struct clk_hw *rate_hw = composite->rate_hw;
+       struct clk_hw *mux_hw = composite->mux_hw;
+
+       if (rate_hw && rate_ops && rate_ops->determine_rate) {
+               rate_hw->clk = hw->clk;
+               return rate_ops->determine_rate(rate_hw, rate, best_parent_rate,
+                                               best_parent_p);
+       } else if (mux_hw && mux_ops && mux_ops->determine_rate) {
+               mux_hw->clk = hw->clk;
+               return mux_ops->determine_rate(rate_hw, rate, best_parent_rate,
+                                              best_parent_p);
+       } else {
+               pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n");
+               return 0;
+       }
+}
+
 static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
                                  unsigned long *prate)
 {
@@ -147,6 +171,8 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
                composite->mux_ops = mux_ops;
                clk_composite_ops->get_parent = clk_composite_get_parent;
                clk_composite_ops->set_parent = clk_composite_set_parent;
+               if (mux_ops->determine_rate)
+                       clk_composite_ops->determine_rate = clk_composite_determine_rate;
        }
 
        if (rate_hw && rate_ops) {
@@ -170,6 +196,8 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
                composite->rate_hw = rate_hw;
                composite->rate_ops = rate_ops;
                clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
+               if (rate_ops->determine_rate)
+                       clk_composite_ops->determine_rate = clk_composite_determine_rate;
        }
 
        if (gate_hw && gate_ops) {

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 2cf2ea6b77a1ac307c22d35aed28b12d7a0da75f..77fcd069c64ae19d085c7fbafe95c9cf7303bd78 100644 (file)
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -272,7 +272,8 @@ static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
        goto out;
 
 err_out:
-       debugfs_remove(clk->dentry);
+       debugfs_remove_recursive(clk->dentry);
+       clk->dentry = NULL;
 out:
        return ret;
 }

diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
index 81dd31a686df9e467b7c111f9c808ee568139551..c3784899f00214bbedd2dcd7d2cbba6e9f0908ae 100644 (file)
--- a/drivers/clk/socfpga/clk.c
+++ b/drivers/clk/socfpga/clk.c
@@ -121,9 +121,7 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
        int rc;
        u32 fixed_div;
 
-       rc = of_property_read_u32(node, "reg", &reg);
-       if (WARN_ON(rc))
-               return NULL;
+       of_property_read_u32(node, "reg", &reg);
 
        socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
        if (WARN_ON(!socfpga_clk))

diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index 88523f91d9b703cc57b1272421fed39430b6f7a6..f05207a27e5f8698d9d68a8f9383e11bef5be8d2 100644 (file)
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -40,7 +40,7 @@ struct clk_factors {
 
 #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
 
-#define SETMASK(len, pos)              (((-1U) >> (31-len))  << (pos))
+#define SETMASK(len, pos)              (((1U << (len)) - 1) << (pos))
 #define CLRMASK(len, pos)              (~(SETMASK(len, pos)))
 #define FACTOR_GET(bit, len, reg)      (((reg) & SETMASK(len, bit)) >> (bit))
 
@@ -88,7 +88,7 @@ static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
 static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
                                unsigned long parent_rate)
 {
-       u8 n, k, m, p;
+       u8 n = 0, k = 0, m = 0, p = 0;
        u32 reg;
        struct clk_factors *factors = to_clk_factors(hw);
        struct clk_factors_config *config = factors->config;

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 9bbd035145409b9908ca25fecfd412d5e7345840..98fec4e4baa76ed5a0077ae57834da8e47c80626 100644 (file)
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -37,18 +37,16 @@ static void __init sun4i_osc_clk_setup(struct device_node *node)
        const char *clk_name = node->name;
        u32 rate;
 
+       if (of_property_read_u32(node, "clock-frequency", &rate))
+               return;
+
        /* allocate fixed-rate and gate clock structs */
        fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
        if (!fixed)
                return;
        gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
-       if (!gate) {
-               kfree(fixed);
-               return;
-       }
-
-       if (of_property_read_u32(node, "clock-frequency", &rate))
-               return;
+       if (!gate)
+               goto err_free_fixed;
 
        /* set up gate and fixed rate properties */
        gate->reg = of_iomap(node, 0);
@@ -63,10 +61,18 @@ static void __init sun4i_osc_clk_setup(struct device_node *node)
                        &gate->hw, &clk_gate_ops,
                        CLK_IS_ROOT);
 
-       if (!IS_ERR(clk)) {
-               of_clk_add_provider(node, of_clk_src_simple_get, clk);
-               clk_register_clkdev(clk, clk_name, NULL);
-       }
+       if (IS_ERR(clk))
+               goto err_free_gate;
+
+       of_clk_add_provider(node, of_clk_src_simple_get, clk);
+       clk_register_clkdev(clk, clk_name, NULL);
+
+       return;
+
+err_free_gate:
+       kfree(gate);
+err_free_fixed:
+       kfree(fixed);
 }
 CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup);
 
@@ -616,7 +622,32 @@ static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_mat
        }
 }
 
-static void __init sunxi_init_clocks(struct device_node *np)
+/**
+ * System clock protection
+ *
+ * By enabling these critical clocks, we prevent their accidental gating
+ * by the framework
+ */
+static void __init sunxi_clock_protect(void)
+{
+       struct clk *clk;
+
+       /* memory bus clock - sun5i+ */
+       clk = clk_get(NULL, "mbus");
+       if (!IS_ERR(clk)) {
+               clk_prepare_enable(clk);
+               clk_put(clk);
+       }
+
+       /* DDR clock - sun4i+ */
+       clk = clk_get(NULL, "pll5_ddr");
+       if (!IS_ERR(clk)) {
+               clk_prepare_enable(clk);
+               clk_put(clk);
+       }
+}
+
+static void __init sunxi_init_clocks(void)
 {
        /* Register factor clocks */
        of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
@@ -629,6 +660,9 @@ static void __init sunxi_init_clocks(struct device_node *np)
 
        /* Register gate clocks */
        of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
+
+       /* Enable core system clocks */
+       sunxi_clock_protect();
 }
 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks);
 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks);