staging: r8188eu: Remove macro ODM_SetRFReg

It is a duplicate of macro PHY_SetRFReg.

Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/rtl8188eu/hal/HalPhyRf_8188e.c b/drivers/staging/rtl8188eu/hal/HalPhyRf_8188e.c
index 1dbe601561b0bad4af67dd7869c9d874b7ae8f2d..9552e4fe4fba20e3c75205ea141fbbfefc2311b5 100644 (file)
--- a/drivers/staging/rtl8188eu/hal/HalPhyRf_8188e.c
+++ b/drivers/staging/rtl8188eu/hal/HalPhyRf_8188e.c
@@ -534,14 +534,14 @@ phy_PathA_RxIQK(struct adapter *adapt, bool configPathB)
        /* modify RXIQK mode table */
        ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n"));
        PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B);
+       PHY_SetRFReg(adapt, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0);
+       PHY_SetRFReg(adapt, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
+       PHY_SetRFReg(adapt, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f);
+       PHY_SetRFReg(adapt, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B);
 
        /* PA,PAD off */
-       ODM_SetRFReg(dm_odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000);
+       PHY_SetRFReg(adapt, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980);
+       PHY_SetRFReg(adapt, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000);
 
        PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
 
@@ -596,10 +596,10 @@ phy_PathA_RxIQK(struct adapter *adapt, bool configPathB)
        /* modify RXIQK mode table */
        ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n"));
        PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa);
+       PHY_SetRFReg(adapt, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0);
+       PHY_SetRFReg(adapt, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
+       PHY_SetRFReg(adapt, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f);
+       PHY_SetRFReg(adapt, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa);
        PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
 
        /* IQK setting */
@@ -637,7 +637,7 @@ phy_PathA_RxIQK(struct adapter *adapt, bool configPathB)
 
        /* reload RF 0xdf */
        PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
-       ODM_SetRFReg(dm_odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180);
+       PHY_SetRFReg(adapt, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180);
 
        if (!(regeac & BIT27) &&                /* if Tx is OK, check whether Rx is OK */
            (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
@@ -1245,18 +1245,18 @@ static void phy_LCCalibrate_8188E(struct adapter *adapt, bool is2t)
 
                /* 2. Set RF mode = standby mode */
                /* Path-A */
-               ODM_SetRFReg(dm_odm, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);
+               PHY_SetRFReg(adapt, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);
 
                /* Path-B */
                if (is2t)
-                       ODM_SetRFReg(dm_odm, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);
+                       PHY_SetRFReg(adapt, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);
        }
 
        /* 3. Read RF reg18 */
        LC_Cal = PHY_QueryRFReg(adapt, RF_PATH_A, RF_CHNLBW, bMask12Bits);
 
        /* 4. Set LC calibration begin  bit15 */
-       ODM_SetRFReg(dm_odm, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
+       PHY_SetRFReg(adapt, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
 
        msleep(100);
 
@@ -1265,11 +1265,11 @@ static void phy_LCCalibrate_8188E(struct adapter *adapt, bool is2t)
                /* Deal with continuous TX case */
                /* Path-A */
                ODM_Write1Byte(dm_odm, 0xd03, tmpreg);
-               ODM_SetRFReg(dm_odm, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
+               PHY_SetRFReg(adapt, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
 
                /* Path-B */
                if (is2t)
-                       ODM_SetRFReg(dm_odm, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
+                       PHY_SetRFReg(adapt, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
        } else {
                /*  Deal with Packet TX case */
                ODM_Write1Byte(dm_odm, REG_TXPAUSE, 0x00);

diff --git a/drivers/staging/rtl8188eu/hal/odm.c b/drivers/staging/rtl8188eu/hal/odm.c
index 18d3a0059bebce5d44d54974ad33c71d24f39b79..00b0675c94c4d509718c3ac10d91d8fe04a8623a 100644 (file)
--- a/drivers/staging/rtl8188eu/hal/odm.c
+++ b/drivers/staging/rtl8188eu/hal/odm.c
@@ -2012,7 +2012,7 @@ bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode)
        PHY_SetBBReg(adapter, rFPGA0_PSDFunction, BIT14|BIT15, 0x0);  /* 128 pts */
 
        /*  To SET CH1 to do */
-       ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01);     /* Channel 1 */
+       PHY_SetRFReg(adapter, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01);     /* Channel 1 */
 
        /*  AFE all on step */
        PHY_SetBBReg(adapter, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4);
@@ -2054,7 +2054,7 @@ bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode)
        PHY_SetBBReg(adapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
 
        /* RF loop Setting */
-       ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
+       PHY_SetRFReg(adapter, RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
 
        /* IQK Single tone start */
        PHY_SetBBReg(adapter, rFPGA0_IQK, bMaskDWord, 0x80800000);
@@ -2101,8 +2101,8 @@ bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode)
        PHY_SetBBReg(adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
        PHY_SetBBReg(adapter, rOFDM0_XAAGCCore1, 0x7F, 0x40);
        PHY_SetBBReg(adapter, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
-       ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
-       ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask, RfLoopReg);
+       PHY_SetRFReg(adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
+       PHY_SetRFReg(adapter, RF_PATH_A, 0x00, bRFRegOffsetMask, RfLoopReg);
 
        /* Reload AFE Registers */
        odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);

diff --git a/drivers/staging/rtl8188eu/hal/odm_RegConfig8188E.c b/drivers/staging/rtl8188eu/hal/odm_RegConfig8188E.c
index eae8358baed51986869b8d6c95e3575b79cad221..0594e70f2a587aa8dfc0694eb6a8fe4fc5306c47 100644 (file)
--- a/drivers/staging/rtl8188eu/hal/odm_RegConfig8188E.c
+++ b/drivers/staging/rtl8188eu/hal/odm_RegConfig8188E.c
@@ -24,7 +24,9 @@ void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr,
                           u32 Data, enum ODM_RF_RADIO_PATH RF_PATH,
                           u32 RegAddr)
 {
-    if (Addr == 0xffe) {
+       struct adapter *adapter = pDM_Odm->Adapter;
+
+       if (Addr == 0xffe) {
                msleep(50);
        } else if (Addr == 0xfd) {
                mdelay(5);
@@ -37,7 +39,7 @@ void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr,
        } else if (Addr == 0xf9) {
                udelay(1);
        } else {
-               ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
+               PHY_SetRFReg(adapter, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
                /*  Add 1us delay between BB/RF register setting. */
                udelay(1);
        }

diff --git a/drivers/staging/rtl8188eu/hal/odm_interface.c b/drivers/staging/rtl8188eu/hal/odm_interface.c
index 68a3391a773ba27fbd75f658118e7e981ceb1117..c2c1d5550418319f3f596016cdb4c59a60f56258 100644 (file)
--- a/drivers/staging/rtl8188eu/hal/odm_interface.c
+++ b/drivers/staging/rtl8188eu/hal/odm_interface.c
@@ -69,12 +69,6 @@ u32 ODM_GetMACReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask)
        return PHY_QueryBBReg(Adapter, RegAddr, BitMask);
 }
 
-void ODM_SetRFReg(struct odm_dm_struct *pDM_Odm, enum ODM_RF_RADIO_PATH        eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
-{
-       struct adapter *Adapter = pDM_Odm->Adapter;
-       PHY_SetRFReg(Adapter, (enum rf_radio_path)eRFPath, RegAddr, BitMask, Data);
-}
-
 u32 ODM_GetRFReg(struct odm_dm_struct *pDM_Odm, enum ODM_RF_RADIO_PATH eRFPath, u32 RegAddr, u32 BitMask)
 {
        struct adapter *Adapter = pDM_Odm->Adapter;

diff --git a/drivers/staging/rtl8188eu/include/odm_interface.h b/drivers/staging/rtl8188eu/include/odm_interface.h
index 65493dd514c3f80da488b4343652102b502e512f..bc13b6aaea23eaef0d44da65e30eb061517f55d0 100644 (file)
--- a/drivers/staging/rtl8188eu/include/odm_interface.h
+++ b/drivers/staging/rtl8188eu/include/odm_interface.h
@@ -94,9 +94,6 @@ void ODM_SetMACReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr,
 
 u32 ODM_GetMACReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask);
 
-void ODM_SetRFReg(struct odm_dm_struct *pDM_Odm, enum ODM_RF_RADIO_PATH eRFPath,
-                 u32 RegAddr, u32 BitMask, u32 Data);
-
 u32 ODM_GetRFReg(struct odm_dm_struct *pDM_Odm, enum ODM_RF_RADIO_PATH eRFPath,
                 u32 RegAddr, u32 BitMask);