]> Pileus Git - ~andy/linux/commitdiff
drm/nouveau: introduce new gart type, and name _SGDMA more appropriately
authorBen Skeggs <bskeggs@redhat.com>
Tue, 11 Jan 2011 04:10:09 +0000 (14:10 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Thu, 24 Feb 2011 20:30:15 +0000 (06:30 +1000)
In preparation for the addition of a new nv40 backend, we'll need to be
able to distinguish between a paged dma object and the on-chip GART.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nouveau_bo.c
drivers/gpu/drm/nouveau/nouveau_drv.h
drivers/gpu/drm/nouveau/nouveau_object.c
drivers/gpu/drm/nouveau/nouveau_sgdma.c

index d38a4d9f9b0b0d6a49c66c3fa01e142e92372f1d..bf260af18b31d8f5e8cda46cb2b6ce27080e1616 100644 (file)
@@ -382,7 +382,8 @@ nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
        case NOUVEAU_GART_AGP:
                return ttm_agp_backend_init(bdev, dev->agp->bridge);
 #endif
-       case NOUVEAU_GART_SGDMA:
+       case NOUVEAU_GART_PDMA:
+       case NOUVEAU_GART_HW:
                return nouveau_sgdma_init_ttm(dev);
        default:
                NV_ERROR(dev, "Unknown GART type %d\n",
@@ -436,7 +437,8 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
                                TTM_PL_FLAG_WC;
                        man->default_caching = TTM_PL_FLAG_WC;
                        break;
-               case NOUVEAU_GART_SGDMA:
+               case NOUVEAU_GART_PDMA:
+               case NOUVEAU_GART_HW:
                        man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
                                     TTM_MEMTYPE_FLAG_CMA;
                        man->available_caching = TTM_PL_MASK_CACHING;
index 9821fcacc3d2f561ed10da893509ac3ace7d5b21..b36dc351f8eb64a7f064ab1103e1e6f7b9004305 100644 (file)
@@ -691,8 +691,9 @@ struct drm_nouveau_private {
        struct {
                enum {
                        NOUVEAU_GART_NONE = 0,
-                       NOUVEAU_GART_AGP,
-                       NOUVEAU_GART_SGDMA
+                       NOUVEAU_GART_AGP,       /* AGP */
+                       NOUVEAU_GART_PDMA,      /* paged dma object */
+                       NOUVEAU_GART_HW         /* on-chip gart/vm */
                } type;
                uint64_t aper_base;
                uint64_t aper_size;
index 03adfe4c76653569a3a7aadcb72420cf3bd2464d..710a7053dc99e47b4e04e80306079ef8fbc67443 100644 (file)
@@ -490,16 +490,22 @@ nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base,
        }
 
        if (target == NV_MEM_TARGET_GART) {
-               if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
-                       target = NV_MEM_TARGET_PCI_NOSNOOP;
-                       base  += dev_priv->gart_info.aper_base;
-               } else
-               if (base != 0) {
-                       base = nouveau_sgdma_get_physical(dev, base);
+               struct nouveau_gpuobj *gart = dev_priv->gart_info.sg_ctxdma;
+
+               if (dev_priv->gart_info.type == NOUVEAU_GART_PDMA) {
+                       if (base == 0) {
+                               nouveau_gpuobj_ref(gart, pobj);
+                               return 0;
+                       }
+
+                       base   = nouveau_sgdma_get_physical(dev, base);
                        target = NV_MEM_TARGET_PCI;
                } else {
-                       nouveau_gpuobj_ref(dev_priv->gart_info.sg_ctxdma, pobj);
-                       return 0;
+                       base += dev_priv->gart_info.aper_base;
+                       if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
+                               target = NV_MEM_TARGET_PCI_NOSNOOP;
+                       else
+                               target = NV_MEM_TARGET_PCI;
                }
        }
 
index a6002f456899f344bf8318ddb89e9153bde479da..fd2093c31e68d569ecc489653e2e59a1a485c6d6 100644 (file)
@@ -237,6 +237,7 @@ nouveau_sgdma_init(struct drm_device *dev)
 
                dev_priv->gart_info.aper_base = dev_priv->gart_info.vma.offset;
                dev_priv->gart_info.aper_size = 512 * 1024 * 1024;
+               dev_priv->gart_info.type = NOUVEAU_GART_HW;
        } else {
                if(dev_priv->ramin_rsvd_vram < 2 * 1024 * 1024)
                        aper_size = 64 * 1024 * 1024;
@@ -266,9 +267,9 @@ nouveau_sgdma_init(struct drm_device *dev)
                dev_priv->gart_info.sg_ctxdma = gpuobj;
                dev_priv->gart_info.aper_base = 0;
                dev_priv->gart_info.aper_size = aper_size;
+               dev_priv->gart_info.type = NOUVEAU_GART_PDMA;
        }
 
-       dev_priv->gart_info.type      = NOUVEAU_GART_SGDMA;
        return 0;
 }