]> Pileus Git - ~andy/linux/commitdiff
Merge tag 'sirf-dts-for-3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua...
authorKevin Hilman <khilman@linaro.org>
Wed, 15 Jan 2014 00:18:35 +0000 (16:18 -0800)
committerKevin Hilman <khilman@linaro.org>
Wed, 15 Jan 2014 00:18:47 +0000 (16:18 -0800)
ARM: sirf: dts update for 3.14

From Barry Song:
some missed dt nodes or props for sirf dts for 3.14.
Among them:
 - add lost clocks for cphifbg
 - add lost bus_width, clock and status for sdhci
 - add clock, frequence-voltage table for CPU0
 - add lost minigpsrtc device node
 - add lost usp1_uart_nostreamctrl pin group for atlas6
 - add pin group for USP0 with only RX or TX frame sync

* tag 'sirf-dts-for-3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux:
  ARM: dts: SiRF: add pin group for USP0 with only RX or TX frame sync
  ARM: dts: SiRF: add lost usp1_uart_nostreamctrl pin group for atlas6
  ARM: dts: sirf: add lost minigpsrtc device node
  ARM: dts: sirf: add clock, frequence-voltage table for CPU0
  ARM: dts: sirf: add lost bus_width, clock and status for sdhci
  ARM: dts: sirf: add lost clocks for cphifbg

Signed-off-by: Kevin Hilman <khilman@linaro.org>
arch/arm/boot/dts/atlas6.dtsi
arch/arm/boot/dts/prima2.dtsi

index 978bab4991dfb03a8a7ce96ea5f7c985ca47daae..f8674bcc4489f0ce09d5409711baddfbb7efae76 100644 (file)
                        timebase-frequency = <0>;
                        bus-frequency = <0>;
                        clock-frequency = <0>;
+                       clocks = <&clks 12>;
+                       operating-points = <
+                               /* kHz    uV */
+                               200000  1025000
+                               400000  1025000
+                               600000  1050000
+                               800000  1100000
+                       >;
+                       clock-latency = <150000>;
                };
        };
 
@@ -69,6 +78,7 @@
                        cphifbg@88030000 {
                                compatible = "sirf,prima2-cphifbg";
                                reg = <0x88030000 0x1000>;
+                               clocks = <&clks 42>;
                        };
                };
 
                                                 sirf,function = "usp1";
                                         };
                                 };
+                               usp1_uart_nostreamctrl_pins_a: usp1@1 {
+                                        usp1 {
+                                                sirf,pins = "usp1_uart_nostreamctrl_grp";
+                                                sirf,function = "usp1_uart_nostreamctrl";
+                                        };
+                                };
                                 usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
                                         usb0_upli_drvbus {
                                                 sirf,pins = "usb0_upli_drvbusgrp";
                                        reg = <0x56100000 0x100000>;
                                        interrupts = <38>;
                                        status = "disabled";
+                                       bus-width = <4>;
                                        clocks = <&clks 36>;
                                };
 
                                        reg = <0x56200000 0x100000>;
                                        interrupts = <23>;
                                        status = "disabled";
+                                       bus-width = <4>;
                                        clocks = <&clks 37>;
                                };
 
                                        reg = <0x56300000 0x100000>;
                                        interrupts = <23>;
                                        status = "disabled";
+                                       bus-width = <4>;
                                        clocks = <&clks 37>;
                                };
 
                                        reg = <0x56500000 0x100000>;
                                        interrupts = <39>;
                                        status = "disabled";
+                                       bus-width = <4>;
                                        clocks = <&clks 38>;
                                };
 
                                interrupts = <52 53 54>;
                        };
 
+                       minigpsrtc@2000 {
+                               compatible = "sirf,prima2-minigpsrtc";
+                               reg = <0x2000 0x1000>;
+                               interrupts = <54>;
+                       };
+
                        pwrc@3000 {
                                compatible = "sirf,prima2-pwrc";
                                reg = <0x3000 0x1000>;
index daee58944e153dac7d2583a849400790daafdb14..0e219932d7cce360ea8011893424ec52979a1bfb 100644 (file)
                        timebase-frequency = <0>;
                        bus-frequency = <0>;
                        clock-frequency = <0>;
+                       clocks = <&clks 12>;
+                       operating-points = <
+                               /* kHz    uV */
+                               200000  1025000
+                               400000  1025000
+                               664000  1050000
+                               800000  1100000
+                       >;
+                       clock-latency = <150000>;
                };
        };
 
@@ -80,6 +89,7 @@
                        cphifbg@88030000 {
                                compatible = "sirf,prima2-cphifbg";
                                reg = <0x88030000 0x1000>;
+                               clocks = <&clks 42>;
                        };
                };
 
                                                        "usp0_uart_nostreamctrl";
                                         };
                                 };
+                                usp0_only_utfs_pins_a: usp0@2 {
+                                        usp0 {
+                                                sirf,pins = "usp0_only_utfs_grp";
+                                                sirf,function = "usp0_only_utfs";
+                                        };
+                                };
+                                usp0_only_urfs_pins_a: usp0@3 {
+                                        usp0 {
+                                                sirf,pins = "usp0_only_urfs_grp";
+                                                sirf,function = "usp0_only_urfs";
+                                        };
+                                };
                                 usp1_pins_a: usp1@0 {
                                         usp1 {
                                                 sirf,pins = "usp1grp";
                                        compatible = "sirf,prima2-sdhc";
                                        reg = <0x56000000 0x100000>;
                                        interrupts = <38>;
+                                       status = "disabled";
+                                       bus-width = <8>;
+                                       clocks = <&clks 36>;
                                };
 
                                sd1: sdhci@56100000 {
                                        compatible = "sirf,prima2-sdhc";
                                        reg = <0x56100000 0x100000>;
                                        interrupts = <38>;
+                                       status = "disabled";
+                                       bus-width = <4>;
+                                       clocks = <&clks 36>;
                                };
 
                                sd2: sdhci@56200000 {
                                        compatible = "sirf,prima2-sdhc";
                                        reg = <0x56200000 0x100000>;
                                        interrupts = <23>;
+                                       status = "disabled";
+                                       clocks = <&clks 37>;
                                };
 
                                sd3: sdhci@56300000 {
                                        compatible = "sirf,prima2-sdhc";
                                        reg = <0x56300000 0x100000>;
                                        interrupts = <23>;
+                                       status = "disabled";
+                                       clocks = <&clks 37>;
                                };
 
                                sd4: sdhci@56400000 {
                                        compatible = "sirf,prima2-sdhc";
                                        reg = <0x56400000 0x100000>;
                                        interrupts = <39>;
+                                       status = "disabled";
+                                       clocks = <&clks 38>;
                                };
 
                                sd5: sdhci@56500000 {
                                        compatible = "sirf,prima2-sdhc";
                                        reg = <0x56500000 0x100000>;
                                        interrupts = <39>;
+                                       clocks = <&clks 38>;
                                };
 
                                pci-copy@57900000 {
                                interrupts = <52 53 54>;
                        };
 
+                       minigpsrtc@2000 {
+                               compatible = "sirf,prima2-minigpsrtc";
+                               reg = <0x2000 0x1000>;
+                               interrupts = <54>;
+                       };
+
                        pwrc@3000 {
                                compatible = "sirf,prima2-pwrc";
                                reg = <0x3000 0x1000>;