obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o
obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o
obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o
+++ obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o
# OMAP voltage domains
voltagedomain-common := voltage.o vc.o vp.o
obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
+++ obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
# OMAP powerdomain framework
powerdomain-common += powerdomain.o powerdomain-common.o
obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o
obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
+++ obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o
+++ obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
# PRCM clockdomain control
clockdomain-common += clockdomain.o
- --clockdomain-common += clockdomains_common_data.o
obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common)
obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common)
obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o
obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
+++ obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o
+++ obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o
obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y)
- --
- --usbfs-$(CONFIG_ARCH_OMAP_OTG) := usb-fs.o
- --obj-y += $(usbfs-m) $(usbfs-y)
obj-y += usb-musb.o
obj-y += omap_phy_internal.o
CLK(NULL, "osc_ck", &osc_ck, CK_242X),
CLK(NULL, "sys_ck", &sys_ck, CK_242X),
CLK(NULL, "alt_ck", &alt_ck, CK_242X),
- -- CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_242X),
- -- CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_242X),
CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X),
/* internal analog sources */
CLK(NULL, "dpll_ck", &dpll_ck, CK_242X),
/* internal prcm root sources */
CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X),
CLK(NULL, "core_ck", &core_ck, CK_242X),
- -- CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_242X),
- -- CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_242X),
CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
CLK(NULL, "pka_ick", &pka_ick, CK_242X),
CLK(NULL, "usb_fck", &usb_fck, CK_242X),
CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
-- - CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.4", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.5", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.6", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.7", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.8", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.9", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.10", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.11", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.12", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.1", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.2", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.3", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.4", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.5", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.6", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.7", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.8", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.9", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.10", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.11", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.12", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.1", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.2", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.3", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.4", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.5", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.6", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.7", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.8", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.9", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.10", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.11", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.12", "alt_ck", &alt_ck, CK_243X),
++ + CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
++ + CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
++ + CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
};
/*
CLK(NULL, "osc_ck", &osc_ck, CK_243X),
CLK(NULL, "sys_ck", &sys_ck, CK_243X),
CLK(NULL, "alt_ck", &alt_ck, CK_243X),
- -- CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_243X),
- -- CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_243X),
- -- CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_243X),
- -- CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_243X),
- -- CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_243X),
CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X),
/* internal analog sources */
CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
/* internal prcm root sources */
CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
CLK(NULL, "core_ck", &core_ck, CK_243X),
- -- CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_243X),
- -- CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_243X),
- -- CLK("omap-mcbsp.3", "prcm_fck", &func_96m_ck, CK_243X),
- -- CLK("omap-mcbsp.4", "prcm_fck", &func_96m_ck, CK_243X),
- -- CLK("omap-mcbsp.5", "prcm_fck", &func_96m_ck, CK_243X),
CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
-- - CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.4", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.5", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.6", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.7", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.8", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.9", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.10", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.11", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.12", "32k_ck", &func_32k_ck, CK_243X),
-- - CLK("omap_timer.1", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.2", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.3", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.4", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.5", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.6", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.7", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.8", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.9", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.10", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.11", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.12", "sys_ck", &sys_ck, CK_243X),
-- - CLK("omap_timer.1", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.2", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.3", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.4", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.5", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.6", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.7", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.8", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.9", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.10", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.11", "alt_ck", &alt_ck, CK_243X),
-- - CLK("omap_timer.12", "alt_ck", &alt_ck, CK_243X),
++ + CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
++ + CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
++ + CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
};
/*
CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
- -- CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_3XXX),
- -- CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_3XXX),
- -- CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_3XXX),
- -- CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_3XXX),
- -- CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_3XXX),
CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
- -- CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
- -- CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
- -- CLK("omap-mcbsp.2", "prcm_fck", &per_96m_fck, CK_3XXX),
- -- CLK("omap-mcbsp.3", "prcm_fck", &per_96m_fck, CK_3XXX),
- -- CLK("omap-mcbsp.4", "prcm_fck", &per_96m_fck, CK_3XXX),
CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
-- - CLK("omap_timer.1", "32k_ck", &omap_32k_fck, CK_3XXX),
-- - CLK("omap_timer.2", "32k_ck", &omap_32k_fck, CK_3XXX),
-- - CLK("omap_timer.3", "32k_ck", &omap_32k_fck, CK_3XXX),
-- - CLK("omap_timer.4", "32k_ck", &omap_32k_fck, CK_3XXX),
-- - CLK("omap_timer.5", "32k_ck", &omap_32k_fck, CK_3XXX),
-- - CLK("omap_timer.6", "32k_ck", &omap_32k_fck, CK_3XXX),
-- - CLK("omap_timer.7", "32k_ck", &omap_32k_fck, CK_3XXX),
-- - CLK("omap_timer.8", "32k_ck", &omap_32k_fck, CK_3XXX),
-- - CLK("omap_timer.9", "32k_ck", &omap_32k_fck, CK_3XXX),
-- - CLK("omap_timer.10", "32k_ck", &omap_32k_fck, CK_3XXX),
-- - CLK("omap_timer.11", "32k_ck", &omap_32k_fck, CK_3XXX),
-- - CLK("omap_timer.12", "32k_ck", &omap_32k_fck, CK_3XXX),
-- - CLK("omap_timer.1", "sys_ck", &sys_ck, CK_3XXX),
-- - CLK("omap_timer.2", "sys_ck", &sys_ck, CK_3XXX),
-- - CLK("omap_timer.3", "sys_ck", &sys_ck, CK_3XXX),
-- - CLK("omap_timer.4", "sys_ck", &sys_ck, CK_3XXX),
-- - CLK("omap_timer.5", "sys_ck", &sys_ck, CK_3XXX),
-- - CLK("omap_timer.6", "sys_ck", &sys_ck, CK_3XXX),
-- - CLK("omap_timer.7", "sys_ck", &sys_ck, CK_3XXX),
-- - CLK("omap_timer.8", "sys_ck", &sys_ck, CK_3XXX),
-- - CLK("omap_timer.9", "sys_ck", &sys_ck, CK_3XXX),
-- - CLK("omap_timer.10", "sys_ck", &sys_ck, CK_3XXX),
-- - CLK("omap_timer.11", "sys_ck", &sys_ck, CK_3XXX),
-- - CLK("omap_timer.12", "sys_ck", &sys_ck, CK_3XXX),
++ + CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX),
++ + CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX),
};
struct omap_clk *c;
u32 cpu_clkflg = 0;
-- if (cpu_is_omap3517()) {
++ if (soc_is_am35xx()) {
cpu_mask = RATE_IN_34XX;
cpu_clkflg = CK_AM35XX;
} else if (cpu_is_omap3630()) {
static struct clk sys_32k_ck = {
.name = "sys_32k_ck",
++ .clkdm_name = "prm_clkdm",
.rate = 32768,
.ops = &clkops_null,
};
.name = "ddrphy_ck",
.parent = &dpll_core_m2_ck,
.ops = &clkops_null,
++ .clkdm_name = "l3_emif_clkdm",
.fixed_div = 2,
.recalc = &omap_fixed_divisor_recalc,
};
static struct clk dpll_mpu_m2_ck = {
.name = "dpll_mpu_m2_ck",
.parent = &dpll_mpu_ck,
++ .clkdm_name = "cm_clkdm",
.clksel = dpll_mpu_m2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
static struct clk l3_div_ck = {
.name = "l3_div_ck",
.parent = &div_core_ck,
++ .clkdm_name = "cm_clkdm",
.clksel = l3_div_div,
.clksel_reg = OMAP4430_CM_CLKSEL_CORE,
.clksel_mask = OMAP4430_CLKSEL_L3_MASK,
static struct clk trace_clk_div_ck = {
.name = "trace_clk_div_ck",
.parent = &pmd_trace_clk_mux_ck,
++ .clkdm_name = "emu_sys_clkdm",
.clksel = trace_clk_div_div,
.clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X),
CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X),
CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
-- - CLK("omap_timer.1", "32k_ck", &sys_32k_ck, CK_443X),
-- - CLK("omap_timer.2", "32k_ck", &sys_32k_ck, CK_443X),
-- - CLK("omap_timer.3", "32k_ck", &sys_32k_ck, CK_443X),
-- - CLK("omap_timer.4", "32k_ck", &sys_32k_ck, CK_443X),
-- - CLK("omap_timer.5", "32k_ck", &sys_32k_ck, CK_443X),
-- - CLK("omap_timer.6", "32k_ck", &sys_32k_ck, CK_443X),
-- - CLK("omap_timer.7", "32k_ck", &sys_32k_ck, CK_443X),
-- - CLK("omap_timer.8", "32k_ck", &sys_32k_ck, CK_443X),
-- - CLK("omap_timer.9", "32k_ck", &sys_32k_ck, CK_443X),
-- - CLK("omap_timer.10", "32k_ck", &sys_32k_ck, CK_443X),
-- - CLK("omap_timer.11", "32k_ck", &sys_32k_ck, CK_443X),
-- - CLK("omap_timer.1", "sys_ck", &sys_clkin_ck, CK_443X),
-- - CLK("omap_timer.2", "sys_ck", &sys_clkin_ck, CK_443X),
-- - CLK("omap_timer.3", "sys_ck", &sys_clkin_ck, CK_443X),
-- - CLK("omap_timer.4", "sys_ck", &sys_clkin_ck, CK_443X),
-- - CLK("omap_timer.9", "sys_ck", &sys_clkin_ck, CK_443X),
-- - CLK("omap_timer.10", "sys_ck", &sys_clkin_ck, CK_443X),
-- - CLK("omap_timer.11", "sys_ck", &sys_clkin_ck, CK_443X),
-- - CLK("omap_timer.5", "sys_ck", &syc_clk_div_ck, CK_443X),
-- - CLK("omap_timer.6", "sys_ck", &syc_clk_div_ck, CK_443X),
-- - CLK("omap_timer.7", "sys_ck", &syc_clk_div_ck, CK_443X),
-- - CLK("omap_timer.8", "sys_ck", &syc_clk_div_ck, CK_443X),
++ + CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X),
++ + CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X),
++ + CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X),
++ + CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X),
++ + CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X),
++ + CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X),
++ + CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X),
++ + CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X),
++ + CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
++ + CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
++ + CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
++ + CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
};
int __init omap4xxx_clk_init(void)
if (cpu_is_omap443x()) {
cpu_mask = RATE_IN_4430;
cpu_clkflg = CK_443X;
--- } else if (cpu_is_omap446x()) {
+++ } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
cpu_mask = RATE_IN_4460 | RATE_IN_4430;
cpu_clkflg = CK_446X | CK_443X;
+++
+++ if (cpu_is_omap447x())
+++ pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
} else {
return 0;
}
extern void __init omap242x_clockdomains_init(void);
extern void __init omap243x_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
+++ extern void __init am33xx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
extern struct clkdm_ops omap2_clkdm_operations;
extern struct clkdm_ops omap3_clkdm_operations;
extern struct clkdm_ops omap4_clkdm_operations;
+++ extern struct clkdm_ops am33xx_clkdm_operations;
extern struct clkdm_dep gfx_24xx_wkdeps[];
extern struct clkdm_dep dsp_24xx_wkdeps[];
extern struct clockdomain wkup_common_clkdm;
- --extern struct clockdomain prm_common_clkdm;
- --extern struct clockdomain cm_common_clkdm;
#endif
#include <mach/ctrl_module_pad_core_44xx.h>
#include <mach/ctrl_module_pad_wkup_44xx.h>
+++ #include <plat/am33xx.h>
+++
#ifndef __ASSEMBLY__
#define OMAP242X_CTRL_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
#define OMAP343X_CTRL_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+++ #define AM33XX_CTRL_REGADDR(reg) \
+++ AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
#else
#define OMAP242X_CTRL_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
#define OMAP343X_CTRL_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+++ #define AM33XX_CTRL_REGADDR(reg) \
+++ AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
#endif /* __ASSEMBLY__ */
/*
OMAP343X_SCRATCHPAD + reg)
/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
--- #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
--- #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1
--- #define AM35XX_VPFE_VBUSP_CLK_SHIFT 2
--- #define AM35XX_HECC_VBUSP_CLK_SHIFT 3
--- #define AM35XX_USBOTG_FCLK_SHIFT 8
--- #define AM35XX_CPGMAC_FCLK_SHIFT 9
--- #define AM35XX_VPFE_FCLK_SHIFT 10
---
--- /*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
+++ #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
+++ #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1
+++ #define AM35XX_VPFE_VBUSP_CLK_SHIFT 2
+++ #define AM35XX_HECC_VBUSP_CLK_SHIFT 3
+++ #define AM35XX_USBOTG_FCLK_SHIFT 8
+++ #define AM35XX_CPGMAC_FCLK_SHIFT 9
+++ #define AM35XX_VPFE_FCLK_SHIFT 10
+++
+++ /* AM35XX CONTROL_LVL_INTR_CLEAR bits */
#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1)
#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2)
#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6)
#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7)
--- /*AM35XX CONTROL_IP_SW_RESET bits*/
+++ /* AM35XX CONTROL_IP_SW_RESET bits */
#define AM35XX_USBOTGSS_SW_RST BIT(0)
#define AM35XX_CPGMACSS_SW_RST BIT(1)
#define AM35XX_VPFE_VBUSP_SW_RST BIT(2)
#define AM35XX_HECC_SW_RST BIT(3)
#define AM35XX_VPFE_PCLK_SW_RST BIT(4)
--- /*
--- * CONTROL AM33XX STATUS register
--- */
+++ /* AM33XX CONTROL_STATUS register */
#define AM33XX_CONTROL_STATUS 0x040
+++ #define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc
--- /*
--- * CONTROL OMAP STATUS register to identify OMAP3 features
--- */
+++ /* AM33XX CONTROL_STATUS bitfields (partial) */
+++ #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22
+++ #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22)
+++
+++ /* CONTROL OMAP STATUS register to identify OMAP3 features */
#define OMAP3_CONTROL_OMAP_STATUS 0x044c
#define OMAP3_SGX_SHIFT 13
extern void omap3_control_save_context(void);
extern void omap3_control_restore_context(void);
extern void omap3_ctrl_write_boot_mode(u8 bootmode);
+ ++extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
+ ++extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
extern void omap3630_ctrl_disable_rta(void);
extern int omap3_ctrl_save_padconf(void);
#else
ct->chip.irq_ack = omap_mask_ack_irq;
ct->chip.irq_mask = irq_gc_mask_disable_reg;
ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
++ ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
ct->regs.enable = INTC_MIR_CLEAR0;
ct->regs.disable = INTC_MIR_SET0;
return 0;
}
--- #ifdef CONFIG_ARCH_OMAP3
+++ #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
void omap_intc_save_context(void)
static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
.name = "timer",
.sysc = &omap3xxx_timer_1ms_sysc,
-- - .rev = OMAP_TIMER_IP_VERSION_1,
};
static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
.name = "timer",
.sysc = &omap3xxx_timer_sysc,
-- - .rev = OMAP_TIMER_IP_VERSION_1,
};
/* secure timers dev attribute */
static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
-- - .timer_capability = OMAP_TIMER_SECURE,
++ + .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
};
/* always-on timers dev attribute */
.idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
},
},
-- - .dev_attr = &capability_alwon_dev_attr,
.class = &omap3xxx_timer_1ms_hwmod_class,
};
.idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
},
},
-- - .dev_attr = &capability_alwon_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
};
.idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
},
},
-- - .dev_attr = &capability_alwon_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
};
.idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
},
},
-- - .dev_attr = &capability_alwon_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
};
.idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
},
},
-- - .dev_attr = &capability_alwon_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
};
.idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
},
},
-- - .dev_attr = &capability_alwon_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
};
.rev = MCBSP_CONFIG_TYPE3,
};
+ ++/* McBSP functional clock mapping */
+ ++static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
+ ++ { .role = "pad_fck", .clk = "mcbsp_clks" },
+ ++ { .role = "prcm_fck", .clk = "core_96m_fck" },
+ ++};
+ ++
+ ++static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
+ ++ { .role = "pad_fck", .clk = "mcbsp_clks" },
+ ++ { .role = "prcm_fck", .clk = "per_96m_fck" },
+ ++};
+ ++
/* mcbsp1 */
static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
{ .name = "common", .irq = 16 },
.idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
},
},
+ ++ .opt_clks = mcbsp15_opt_clks,
+ ++ .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
};
/* mcbsp2 */
.idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
},
},
+ ++ .opt_clks = mcbsp234_opt_clks,
+ ++ .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
.dev_attr = &omap34xx_mcbsp2_dev_attr,
};
.idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
},
},
+ ++ .opt_clks = mcbsp234_opt_clks,
+ ++ .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
.dev_attr = &omap34xx_mcbsp3_dev_attr,
};
.idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
},
},
+ ++ .opt_clks = mcbsp234_opt_clks,
+ ++ .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
};
/* mcbsp5 */
.idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
},
},
+ ++ .opt_clks = mcbsp15_opt_clks,
+ ++ .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
};
/* 'mcbsp sidetone' class */
struct omap_hwmod_ocp_if **h = NULL;
unsigned int rev;
+ ++ omap_hwmod_init();
+ ++
/* Register hwmod links common to all OMAP3 */
r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
if (r < 0)
.rev_offs = 0x0000,
.sysc_offs = 0x0004,
.sysc_flags = SYSC_HAS_SIDLEMODE,
-- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-- SIDLE_SMART_WKUP),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO),
.sysc_fields = &omap_hwmod_sysc_type1,
};
.name = "dss_hdmi",
.class = &omap44xx_hdmi_hwmod_class,
.clkdm_name = "l3_dss_clkdm",
++ /*
++ * HDMI audio requires to use no-idle mode. Hence,
++ * set idle mode by software.
++ */
++ .flags = HWMOD_SWSUP_SIDLE,
.mpu_irqs = omap44xx_dss_hdmi_irqs,
.sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
.main_clk = "dss_48mhz_clk",
static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
.name = "cm_core_aon",
.class = &omap44xx_prcm_hwmod_class,
- -- .clkdm_name = "cm_clkdm",
};
/* cm_core */
static struct omap_hwmod omap44xx_cm_core_hwmod = {
.name = "cm_core",
.class = &omap44xx_prcm_hwmod_class,
- -- .clkdm_name = "cm_clkdm",
};
/* prm */
static struct omap_hwmod omap44xx_prm_hwmod = {
.name = "prm",
.class = &omap44xx_prcm_hwmod_class,
- -- .clkdm_name = "prm_clkdm",
.mpu_irqs = omap44xx_prm_irqs,
.rst_lines = omap44xx_prm_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
.modulemode = MODULEMODE_SWCTRL,
},
},
-- - .dev_attr = &capability_alwon_dev_attr,
};
/* timer3 */
.modulemode = MODULEMODE_SWCTRL,
},
},
-- - .dev_attr = &capability_alwon_dev_attr,
};
/* timer4 */
.modulemode = MODULEMODE_SWCTRL,
},
},
-- - .dev_attr = &capability_alwon_dev_attr,
};
/* timer5 */
.modulemode = MODULEMODE_SWCTRL,
},
},
-- - .dev_attr = &capability_alwon_dev_attr,
};
/* timer6 */
.modulemode = MODULEMODE_SWCTRL,
},
},
-- - .dev_attr = &capability_alwon_dev_attr,
};
/* timer7 */
.modulemode = MODULEMODE_SWCTRL,
},
},
-- - .dev_attr = &capability_alwon_dev_attr,
};
/* timer8 */
int __init omap44xx_hwmod_init(void)
{
+ ++ omap_hwmod_init();
return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
}
#define OMAP3_SECURE_TIMER 1
#endif
-- -/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
-- -#define MAX_GPTIMER_ID 12
-- -
-- -static u32 sys_timer_reserved;
-- -
/* Clockevent code */
static struct omap_dm_timer clkev;
omap_hwmod_enable(oh);
-- - sys_timer_reserved |= (1 << (gptimer_id - 1));
++ + if (omap_dm_timer_reserve_systimer(gptimer_id))
++ + return -ENODEV;
if (gptimer_id != 12) {
struct clk *src;
OMAP_SYS_TIMER(3_secure)
#endif
+++ #ifdef CONFIG_SOC_AM33XX
+++ OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
+++ OMAP_SYS_TIMER(3_am33xx)
+++ #endif
+++
#ifdef CONFIG_ARCH_OMAP4
#ifdef CONFIG_LOCAL_TIMERS
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
OMAP_SYS_TIMER(4)
#endif
-- -/**
-- - * omap2_dm_timer_set_src - change the timer input clock source
-- - * @pdev: timer platform device pointer
-- - * @source: array index of parent clock source
-- - */
-- -static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
-- -{
-- - int ret;
-- - struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
-- - struct clk *fclk, *parent;
-- - char *parent_name = NULL;
-- -
-- - fclk = clk_get(&pdev->dev, "fck");
-- - if (IS_ERR_OR_NULL(fclk)) {
-- - dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
-- - __func__, __LINE__);
-- - return -EINVAL;
-- - }
-- -
-- - switch (source) {
-- - case OMAP_TIMER_SRC_SYS_CLK:
-- - parent_name = "sys_ck";
-- - break;
-- -
-- - case OMAP_TIMER_SRC_32_KHZ:
-- - parent_name = "32k_ck";
-- - break;
-- -
-- - case OMAP_TIMER_SRC_EXT_CLK:
-- - if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
-- - parent_name = "alt_ck";
-- - break;
-- - }
-- - dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
-- - __func__, __LINE__);
-- - clk_put(fclk);
-- - return -EINVAL;
-- - }
-- -
-- - parent = clk_get(&pdev->dev, parent_name);
-- - if (IS_ERR_OR_NULL(parent)) {
-- - dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
-- - __func__, __LINE__, parent_name);
-- - clk_put(fclk);
-- - return -EINVAL;
-- - }
-- -
-- - ret = clk_set_parent(fclk, parent);
-- - if (IS_ERR_VALUE(ret)) {
-- - dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
-- - __func__, parent_name);
-- - ret = -EINVAL;
-- - }
-- -
-- - clk_put(parent);
-- - clk_put(fclk);
-- -
-- - return ret;
-- -}
-- -
/**
* omap_timer_init - build and register timer device with an
* associated timer hwmod
struct dmtimer_platform_data *pdata;
struct platform_device *pdev;
struct omap_timer_capability_dev_attr *timer_dev_attr;
-- - struct powerdomain *pwrdm;
pr_debug("%s: %s\n", __func__, oh->name);
*/
sscanf(oh->name, "timer%2d", &id);
-- - pdata->set_timer_src = omap2_dm_timer_set_src;
-- - pdata->timer_ip_version = oh->class->rev;
-- -
-- - /* Mark clocksource and clockevent timers as reserved */
-- - if ((sys_timer_reserved >> (id - 1)) & 0x1)
-- - pdata->reserved = 1;
++ + if (timer_dev_attr)
++ + pdata->timer_capability = timer_dev_attr->timer_capability;
-- - pwrdm = omap_hwmod_get_pwrdm(oh);
-- - pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
-- -#ifdef CONFIG_PM
-- - pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
-- -#endif
pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
NULL, 0, 0);
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