]> Pileus Git - ~andy/linux/commitdiff
drm/i915/bdw: Limit GTT to 2GB
authorBen Widawsky <benjamin.widawsky@intel.com>
Fri, 8 Nov 2013 05:40:51 +0000 (21:40 -0800)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 14 Nov 2013 08:33:11 +0000 (09:33 +0100)
Because of the way in which we're allocating the pages for the Aliasing
PPGTT, we cannot actually successfully alloc enough space for anything
greater than 2GB.

Instead of a quick hack to fix this, we should defer until we have the
real solution in place (allocating much less contiguous space).

This wasn't found sooner because we didn't not have any systems
supporting more than a 2GB GTT.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_gem_gtt.c

index 5a3cc3189f1fd6545b1e0c79ca1ea0598d9a5f72..f69bdc741b8008729747feccc2cb66b6cc75f4af 100644 (file)
@@ -1239,6 +1239,11 @@ static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
        bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
        if (bdw_gmch_ctl)
                bdw_gmch_ctl = 1 << bdw_gmch_ctl;
+       if (bdw_gmch_ctl > 4) {
+               WARN_ON(!i915_preliminary_hw_support);
+               return 4<<20;
+       }
+
        return bdw_gmch_ctl << 20;
 }