]> Pileus Git - ~andy/linux/commitdiff
x86/mce: Update MCE severity condition check
authorChen Gong <gong.chen@linux.intel.com>
Thu, 20 Jun 2013 09:16:12 +0000 (05:16 -0400)
committerTony Luck <tony.luck@intel.com>
Thu, 27 Jun 2013 20:45:52 +0000 (13:45 -0700)
Update some SRAR severity conditions check to make it clearer,
according to latest Intel SDM Vol 3(June 2013), table 15-20.

Signed-off-by: Chen Gong <gong.chen@linux.intel.com>
Acked-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
arch/x86/kernel/cpu/mcheck/mce-severity.c

index beb1f1689e5261b1dca299ea3cd442133843ca40..e2703520d1208539d21447d6f570a767b7e51f48 100644 (file)
@@ -110,22 +110,17 @@ static struct severity {
        /* known AR MCACODs: */
 #ifdef CONFIG_MEMORY_FAILURE
        MCESEV(
-               KEEP, "HT thread notices Action required: data load error",
-               SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
-               MCGMASK(MCG_STATUS_EIPV, 0)
+               KEEP, "Action required but unaffected thread is continuable",
+               SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR),
+               MCGMASK(MCG_STATUS_RIPV, MCG_STATUS_RIPV)
                ),
        MCESEV(
-               AR, "Action required: data load error",
+               AR, "Action required: data load error in a user process",
                SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
                USER
                ),
        MCESEV(
-               KEEP, "HT thread notices Action required: instruction fetch error",
-               SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),
-               MCGMASK(MCG_STATUS_EIPV, 0)
-               ),
-       MCESEV(
-               AR, "Action required: instruction fetch error",
+               AR, "Action required: instruction fetch error in a user process",
                SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),
                USER
                ),