sata, highbank: send extra clock cycles in SGPIO patterns

Some SGPIO PICs don't follow the standard very well and expect a certain
number of clock cycles or port frames in each SGPIO pattern. Add two
optional parameters in the DTB that can provide the number of extra
clock cycles to be sent before and after SGPIO pattern. Read those
parameters from the DTB and send the extra clock cycles.

Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Tejun Heo <tj@kernel.org>

diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt
index c84833e133637fb132142d17b453f737864d7e58..aa83407cb7a4404e0cc57f20d13f81c9cc749230 100644 (file)
--- a/Documentation/devicetree/bindings/ata/sata_highbank.txt
+++ b/Documentation/devicetree/bindings/ata/sata_highbank.txt
@@ -23,6 +23,10 @@ Optional properties:
 - calxeda,tx-atten  : a u32 array that contains TX attenuation override
                        codes, one per port. The upper 3 bytes are always
                        0 and thus ignored.
+- calxeda,pre-clocks : a u32 that indicates the number of additional clock
+                       cycles to transmit before sending an SGPIO pattern
+- calxeda,post-clocks: a u32 that indicates the number of additional clock
+                       cycles to transmit after sending an SGPIO pattern
 
 Example:
         sata@ffe08000 {
@@ -35,4 +39,6 @@ Example:
                calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
                calxeda,led-order = <4 0 1 2 3>;
                calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
+               calxeda,pre-clocks = <10>;
+               calxeda,post-clocks = <0>;
         };

diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
index ba43c72175455ca074e3243b69a3b9520bb741c1..0849672218c90c5d6abfe9e32ba6ccc70827de6f 100644 (file)
--- a/drivers/ata/sata_highbank.c
+++ b/drivers/ata/sata_highbank.c
@@ -84,6 +84,9 @@ static DEFINE_SPINLOCK(sgpio_lock);
 
 struct ecx_plat_data {
        u32             n_ports;
+       /* number of extra clocks that the SGPIO PIC controller expects */
+       u32             pre_clocks;
+       u32             post_clocks;
        unsigned        sgpio_gpio[SGPIO_PINS];
        u32             sgpio_pattern;
        u32             port_to_sgpio[SGPIO_PORTS];
@@ -160,6 +163,9 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
        spin_lock_irqsave(&sgpio_lock, flags);
        ecx_parse_sgpio(pdata, ap->port_no, state);
        sgpio_out = pdata->sgpio_pattern;
+       for (i = 0; i < pdata->pre_clocks; i++)
+               ecx_led_cycle_clock(pdata);
+
        gpio_set_value(pdata->sgpio_gpio[SLOAD], 1);
        ecx_led_cycle_clock(pdata);
        gpio_set_value(pdata->sgpio_gpio[SLOAD], 0);
@@ -172,6 +178,8 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
                sgpio_out >>= 1;
                ecx_led_cycle_clock(pdata);
        }
+       for (i = 0; i < pdata->post_clocks; i++)
+               ecx_led_cycle_clock(pdata);
 
        /* save off new led state for port/slot */
        emp->led_state = state;
@@ -206,6 +214,11 @@ static void highbank_set_em_messages(struct device *dev,
        of_property_read_u32_array(np, "calxeda,led-order",
                                                pdata->port_to_sgpio,
                                                pdata->n_ports);
+       if (of_property_read_u32(np, "calxeda,pre-clocks", &pdata->pre_clocks))
+               pdata->pre_clocks = 0;
+       if (of_property_read_u32(np, "calxeda,post-clocks",
+                               &pdata->post_clocks))
+               pdata->post_clocks = 0;
 
        /* store em_loc */
        hpriv->em_loc = 0;