dma: coh901318: push platform data into driver

We're only ever going to support the U300 with this driver
so skip the separation of platform data from driver, and push
it down into the driver itself.

Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 0951b51f36a686f9501cf066bc4b477bf39ab557..834d0bd2aa0ff28405b51768ea64b3e0d6e518bd 100644 (file)
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -327,1089 +327,6 @@ static struct resource dma_resource[] = {
        }
 };
 
-/* points out all dma slave channels.
- * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
- * Select all channels from A to B, end of list is marked with -1,-1
- */
-static int dma_slave_channels[] = {
-       U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
-       U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
-
-/* points out all dma memcpy channels. */
-static int dma_memcpy_channels[] = {
-       U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
-
-/** register dma for memory access
- *
- * active  1 means dma intends to access memory
- *         0 means dma wont access memory
- */
-static void coh901318_access_memory_state(struct device *dev, bool active)
-{
-}
-
-#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
-                       COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
-                       COH901318_CX_CFG_LCR_DISABLE | \
-                       COH901318_CX_CFG_TC_IRQ_ENABLE | \
-                       COH901318_CX_CFG_BE_IRQ_ENABLE)
-#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
-                       COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
-                       COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
-                       COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
-                       COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
-                       COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
-                       COH901318_CX_CTRL_MASTER_MODE_M1RW | \
-                       COH901318_CX_CTRL_TCP_DISABLE | \
-                       COH901318_CX_CTRL_TC_IRQ_DISABLE | \
-                       COH901318_CX_CTRL_HSP_DISABLE | \
-                       COH901318_CX_CTRL_HSS_DISABLE | \
-                       COH901318_CX_CTRL_DDMA_LEGACY | \
-                       COH901318_CX_CTRL_PRDD_SOURCE)
-#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
-                       COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
-                       COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
-                       COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
-                       COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
-                       COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
-                       COH901318_CX_CTRL_MASTER_MODE_M1RW | \
-                       COH901318_CX_CTRL_TCP_DISABLE | \
-                       COH901318_CX_CTRL_TC_IRQ_DISABLE | \
-                       COH901318_CX_CTRL_HSP_DISABLE | \
-                       COH901318_CX_CTRL_HSS_DISABLE | \
-                       COH901318_CX_CTRL_DDMA_LEGACY | \
-                       COH901318_CX_CTRL_PRDD_SOURCE)
-#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
-                       COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
-                       COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
-                       COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
-                       COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
-                       COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
-                       COH901318_CX_CTRL_MASTER_MODE_M1RW | \
-                       COH901318_CX_CTRL_TCP_DISABLE | \
-                       COH901318_CX_CTRL_TC_IRQ_ENABLE | \
-                       COH901318_CX_CTRL_HSP_DISABLE | \
-                       COH901318_CX_CTRL_HSS_DISABLE | \
-                       COH901318_CX_CTRL_DDMA_LEGACY | \
-                       COH901318_CX_CTRL_PRDD_SOURCE)
-
-const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
-       {
-               .number = U300_DMA_MSL_TX_0,
-               .name = "MSL TX 0",
-               .priority_high = 0,
-               .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
-       },
-       {
-               .number = U300_DMA_MSL_TX_1,
-               .name = "MSL TX 1",
-               .priority_high = 0,
-               .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
-               .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_LCR_DISABLE |
-                               COH901318_CX_CFG_TC_IRQ_ENABLE |
-                               COH901318_CX_CFG_BE_IRQ_ENABLE,
-               .param.ctrl_lli_chained = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_SOURCE,
-               .param.ctrl_lli = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_SOURCE,
-               .param.ctrl_lli_last = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_SOURCE,
-       },
-       {
-               .number = U300_DMA_MSL_TX_2,
-               .name = "MSL TX 2",
-               .priority_high = 0,
-               .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
-               .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_LCR_DISABLE |
-                               COH901318_CX_CFG_TC_IRQ_ENABLE |
-                               COH901318_CX_CFG_BE_IRQ_ENABLE,
-               .param.ctrl_lli_chained = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_SOURCE,
-               .param.ctrl_lli = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_SOURCE,
-               .param.ctrl_lli_last = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_SOURCE,
-               .desc_nbr_max = 10,
-       },
-       {
-               .number = U300_DMA_MSL_TX_3,
-               .name = "MSL TX 3",
-               .priority_high = 0,
-               .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
-               .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_LCR_DISABLE |
-                               COH901318_CX_CFG_TC_IRQ_ENABLE |
-                               COH901318_CX_CFG_BE_IRQ_ENABLE,
-               .param.ctrl_lli_chained = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_SOURCE,
-               .param.ctrl_lli = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_SOURCE,
-               .param.ctrl_lli_last = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_SOURCE,
-       },
-       {
-               .number = U300_DMA_MSL_TX_4,
-               .name = "MSL TX 4",
-               .priority_high = 0,
-               .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
-               .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_LCR_DISABLE |
-                               COH901318_CX_CFG_TC_IRQ_ENABLE |
-                               COH901318_CX_CFG_BE_IRQ_ENABLE,
-               .param.ctrl_lli_chained = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_SOURCE,
-               .param.ctrl_lli = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_SOURCE,
-               .param.ctrl_lli_last = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_SOURCE,
-       },
-       {
-               .number = U300_DMA_MSL_TX_5,
-               .name = "MSL TX 5",
-               .priority_high = 0,
-               .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
-       },
-       {
-               .number = U300_DMA_MSL_TX_6,
-               .name = "MSL TX 6",
-               .priority_high = 0,
-               .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
-       },
-       {
-               .number = U300_DMA_MSL_RX_0,
-               .name = "MSL RX 0",
-               .priority_high = 0,
-               .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
-       },
-       {
-               .number = U300_DMA_MSL_RX_1,
-               .name = "MSL RX 1",
-               .priority_high = 0,
-               .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
-               .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_LCR_DISABLE |
-                               COH901318_CX_CFG_TC_IRQ_ENABLE |
-                               COH901318_CX_CFG_BE_IRQ_ENABLE,
-               .param.ctrl_lli_chained = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                               COH901318_CX_CTRL_PRDD_DEST,
-               .param.ctrl_lli = 0,
-               .param.ctrl_lli_last = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                               COH901318_CX_CTRL_PRDD_DEST,
-       },
-       {
-               .number = U300_DMA_MSL_RX_2,
-               .name = "MSL RX 2",
-               .priority_high = 0,
-               .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
-               .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_LCR_DISABLE |
-                               COH901318_CX_CFG_TC_IRQ_ENABLE |
-                               COH901318_CX_CFG_BE_IRQ_ENABLE,
-               .param.ctrl_lli_chained = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                               COH901318_CX_CTRL_PRDD_DEST,
-               .param.ctrl_lli = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                               COH901318_CX_CTRL_PRDD_DEST,
-               .param.ctrl_lli_last = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                               COH901318_CX_CTRL_PRDD_DEST,
-       },
-       {
-               .number = U300_DMA_MSL_RX_3,
-               .name = "MSL RX 3",
-               .priority_high = 0,
-               .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
-               .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_LCR_DISABLE |
-                               COH901318_CX_CFG_TC_IRQ_ENABLE |
-                               COH901318_CX_CFG_BE_IRQ_ENABLE,
-               .param.ctrl_lli_chained = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                               COH901318_CX_CTRL_PRDD_DEST,
-               .param.ctrl_lli = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                               COH901318_CX_CTRL_PRDD_DEST,
-               .param.ctrl_lli_last = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                               COH901318_CX_CTRL_PRDD_DEST,
-       },
-       {
-               .number = U300_DMA_MSL_RX_4,
-               .name = "MSL RX 4",
-               .priority_high = 0,
-               .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
-               .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_LCR_DISABLE |
-                               COH901318_CX_CFG_TC_IRQ_ENABLE |
-                               COH901318_CX_CFG_BE_IRQ_ENABLE,
-               .param.ctrl_lli_chained = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                               COH901318_CX_CTRL_PRDD_DEST,
-               .param.ctrl_lli = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                               COH901318_CX_CTRL_PRDD_DEST,
-               .param.ctrl_lli_last = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                               COH901318_CX_CTRL_PRDD_DEST,
-       },
-       {
-               .number = U300_DMA_MSL_RX_5,
-               .name = "MSL RX 5",
-               .priority_high = 0,
-               .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
-               .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_LCR_DISABLE |
-                               COH901318_CX_CFG_TC_IRQ_ENABLE |
-                               COH901318_CX_CFG_BE_IRQ_ENABLE,
-               .param.ctrl_lli_chained = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                               COH901318_CX_CTRL_PRDD_DEST,
-               .param.ctrl_lli = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                               COH901318_CX_CTRL_PRDD_DEST,
-               .param.ctrl_lli_last = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
-                               COH901318_CX_CTRL_PRDD_DEST,
-       },
-       {
-               .number = U300_DMA_MSL_RX_6,
-               .name = "MSL RX 6",
-               .priority_high = 0,
-               .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
-       },
-       /*
-        * Don't set up device address, burst count or size of src
-        * or dst bus for this peripheral - handled by PrimeCell
-        * DMA extension.
-        */
-       {
-               .number = U300_DMA_MMCSD_RX_TX,
-               .name = "MMCSD RX TX",
-               .priority_high = 0,
-               .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_LCR_DISABLE |
-                               COH901318_CX_CFG_TC_IRQ_ENABLE |
-                               COH901318_CX_CFG_BE_IRQ_ENABLE,
-               .param.ctrl_lli_chained = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY,
-               .param.ctrl_lli = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY,
-               .param.ctrl_lli_last = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY,
-
-       },
-       {
-               .number = U300_DMA_MSPRO_TX,
-               .name = "MSPRO TX",
-               .priority_high = 0,
-       },
-       {
-               .number = U300_DMA_MSPRO_RX,
-               .name = "MSPRO RX",
-               .priority_high = 0,
-       },
-       /*
-        * Don't set up device address, burst count or size of src
-        * or dst bus for this peripheral - handled by PrimeCell
-        * DMA extension.
-        */
-       {
-               .number = U300_DMA_UART0_TX,
-               .name = "UART0 TX",
-               .priority_high = 0,
-               .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_LCR_DISABLE |
-                               COH901318_CX_CFG_TC_IRQ_ENABLE |
-                               COH901318_CX_CFG_BE_IRQ_ENABLE,
-               .param.ctrl_lli_chained = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY,
-               .param.ctrl_lli = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY,
-               .param.ctrl_lli_last = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY,
-       },
-       {
-               .number = U300_DMA_UART0_RX,
-               .name = "UART0 RX",
-               .priority_high = 0,
-               .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_LCR_DISABLE |
-                               COH901318_CX_CFG_TC_IRQ_ENABLE |
-                               COH901318_CX_CFG_BE_IRQ_ENABLE,
-               .param.ctrl_lli_chained = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY,
-               .param.ctrl_lli = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY,
-               .param.ctrl_lli_last = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY,
-       },
-       {
-               .number = U300_DMA_APEX_TX,
-               .name = "APEX TX",
-               .priority_high = 0,
-       },
-       {
-               .number = U300_DMA_APEX_RX,
-               .name = "APEX RX",
-               .priority_high = 0,
-       },
-       {
-               .number = U300_DMA_PCM_I2S0_TX,
-               .name = "PCM I2S0 TX",
-               .priority_high = 1,
-               .dev_addr = U300_PCM_I2S0_BASE + 0x14,
-               .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_LCR_DISABLE |
-                               COH901318_CX_CFG_TC_IRQ_ENABLE |
-                               COH901318_CX_CFG_BE_IRQ_ENABLE,
-               .param.ctrl_lli_chained = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_SOURCE,
-               .param.ctrl_lli = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_SOURCE,
-               .param.ctrl_lli_last = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_SOURCE,
-       },
-       {
-               .number = U300_DMA_PCM_I2S0_RX,
-               .name = "PCM I2S0 RX",
-               .priority_high = 1,
-               .dev_addr = U300_PCM_I2S0_BASE + 0x10,
-               .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_LCR_DISABLE |
-                               COH901318_CX_CFG_TC_IRQ_ENABLE |
-                               COH901318_CX_CFG_BE_IRQ_ENABLE,
-               .param.ctrl_lli_chained = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_DEST,
-               .param.ctrl_lli = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_DEST,
-               .param.ctrl_lli_last = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_DEST,
-       },
-       {
-               .number = U300_DMA_PCM_I2S1_TX,
-               .name = "PCM I2S1 TX",
-               .priority_high = 1,
-               .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
-               .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_LCR_DISABLE |
-                               COH901318_CX_CFG_TC_IRQ_ENABLE |
-                               COH901318_CX_CFG_BE_IRQ_ENABLE,
-               .param.ctrl_lli_chained = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_SOURCE,
-               .param.ctrl_lli = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_SOURCE,
-               .param.ctrl_lli_last = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_SOURCE,
-       },
-       {
-               .number = U300_DMA_PCM_I2S1_RX,
-               .name = "PCM I2S1 RX",
-               .priority_high = 1,
-               .dev_addr = U300_PCM_I2S1_BASE + 0x10,
-               .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_LCR_DISABLE |
-                               COH901318_CX_CFG_TC_IRQ_ENABLE |
-                               COH901318_CX_CFG_BE_IRQ_ENABLE,
-               .param.ctrl_lli_chained = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_DEST,
-               .param.ctrl_lli = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_DEST,
-               .param.ctrl_lli_last = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
-                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
-                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
-                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY |
-                               COH901318_CX_CTRL_PRDD_DEST,
-       },
-       {
-               .number = U300_DMA_XGAM_CDI,
-               .name = "XGAM CDI",
-               .priority_high = 0,
-       },
-       {
-               .number = U300_DMA_XGAM_PDI,
-               .name = "XGAM PDI",
-               .priority_high = 0,
-       },
-       /*
-        * Don't set up device address, burst count or size of src
-        * or dst bus for this peripheral - handled by PrimeCell
-        * DMA extension.
-        */
-       {
-               .number = U300_DMA_SPI_TX,
-               .name = "SPI TX",
-               .priority_high = 0,
-               .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_LCR_DISABLE |
-                               COH901318_CX_CFG_TC_IRQ_ENABLE |
-                               COH901318_CX_CFG_BE_IRQ_ENABLE,
-               .param.ctrl_lli_chained = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY,
-               .param.ctrl_lli = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY,
-               .param.ctrl_lli_last = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY,
-       },
-       {
-               .number = U300_DMA_SPI_RX,
-               .name = "SPI RX",
-               .priority_high = 0,
-               .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_LCR_DISABLE |
-                               COH901318_CX_CFG_TC_IRQ_ENABLE |
-                               COH901318_CX_CFG_BE_IRQ_ENABLE,
-               .param.ctrl_lli_chained = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY,
-               .param.ctrl_lli = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY,
-               .param.ctrl_lli_last = 0 |
-                               COH901318_CX_CTRL_TC_ENABLE |
-                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
-                               COH901318_CX_CTRL_HSP_ENABLE |
-                               COH901318_CX_CTRL_HSS_DISABLE |
-                               COH901318_CX_CTRL_DDMA_LEGACY,
-
-       },
-       {
-               .number = U300_DMA_GENERAL_PURPOSE_0,
-               .name = "GENERAL 00",
-               .priority_high = 0,
-
-               .param.config = flags_memcpy_config,
-               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-               .param.ctrl_lli = flags_memcpy_lli,
-               .param.ctrl_lli_last = flags_memcpy_lli_last,
-       },
-       {
-               .number = U300_DMA_GENERAL_PURPOSE_1,
-               .name = "GENERAL 01",
-               .priority_high = 0,
-
-               .param.config = flags_memcpy_config,
-               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-               .param.ctrl_lli = flags_memcpy_lli,
-               .param.ctrl_lli_last = flags_memcpy_lli_last,
-       },
-       {
-               .number = U300_DMA_GENERAL_PURPOSE_2,
-               .name = "GENERAL 02",
-               .priority_high = 0,
-
-               .param.config = flags_memcpy_config,
-               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-               .param.ctrl_lli = flags_memcpy_lli,
-               .param.ctrl_lli_last = flags_memcpy_lli_last,
-       },
-       {
-               .number = U300_DMA_GENERAL_PURPOSE_3,
-               .name = "GENERAL 03",
-               .priority_high = 0,
-
-               .param.config = flags_memcpy_config,
-               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-               .param.ctrl_lli = flags_memcpy_lli,
-               .param.ctrl_lli_last = flags_memcpy_lli_last,
-       },
-       {
-               .number = U300_DMA_GENERAL_PURPOSE_4,
-               .name = "GENERAL 04",
-               .priority_high = 0,
-
-               .param.config = flags_memcpy_config,
-               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-               .param.ctrl_lli = flags_memcpy_lli,
-               .param.ctrl_lli_last = flags_memcpy_lli_last,
-       },
-       {
-               .number = U300_DMA_GENERAL_PURPOSE_5,
-               .name = "GENERAL 05",
-               .priority_high = 0,
-
-               .param.config = flags_memcpy_config,
-               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-               .param.ctrl_lli = flags_memcpy_lli,
-               .param.ctrl_lli_last = flags_memcpy_lli_last,
-       },
-       {
-               .number = U300_DMA_GENERAL_PURPOSE_6,
-               .name = "GENERAL 06",
-               .priority_high = 0,
-
-               .param.config = flags_memcpy_config,
-               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-               .param.ctrl_lli = flags_memcpy_lli,
-               .param.ctrl_lli_last = flags_memcpy_lli_last,
-       },
-       {
-               .number = U300_DMA_GENERAL_PURPOSE_7,
-               .name = "GENERAL 07",
-               .priority_high = 0,
-
-               .param.config = flags_memcpy_config,
-               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-               .param.ctrl_lli = flags_memcpy_lli,
-               .param.ctrl_lli_last = flags_memcpy_lli_last,
-       },
-       {
-               .number = U300_DMA_GENERAL_PURPOSE_8,
-               .name = "GENERAL 08",
-               .priority_high = 0,
-
-               .param.config = flags_memcpy_config,
-               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-               .param.ctrl_lli = flags_memcpy_lli,
-               .param.ctrl_lli_last = flags_memcpy_lli_last,
-       },
-       {
-               .number = U300_DMA_UART1_TX,
-               .name = "UART1 TX",
-               .priority_high = 0,
-       },
-       {
-               .number = U300_DMA_UART1_RX,
-               .name = "UART1 RX",
-               .priority_high = 0,
-       }
-};
-
-
-static struct coh901318_platform coh901318_platform = {
-       .chans_slave = dma_slave_channels,
-       .chans_memcpy = dma_memcpy_channels,
-       .access_memory_state = coh901318_access_memory_state,
-       .chan_conf = chan_config,
-       .max_channels = U300_DMA_CHANNELS,
-};
 
 static struct resource pinctrl_resources[] = {
        {
@@ -1521,7 +438,6 @@ static struct platform_device dma_device = {
        .resource       = dma_resource,
        .num_resources  = ARRAY_SIZE(dma_resource),
        .dev = {
-               .platform_data = &coh901318_platform,
                .coherent_dma_mask = ~0,
        },
 };

diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 5fdd38bcda23a023f48b2c7817ca120ab9e612d8..06d97955c544547190e1e8620edd0cc0aafbda90 100644 (file)
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -23,10 +23,1094 @@
 #include <linux/debugfs.h>
 #include <linux/platform_data/dma-coh901318.h>
 #include <mach/coh901318.h>
+#include <mach/u300-regs.h>
 
 #include "coh901318_lli.h"
 #include "dmaengine.h"
 
+/* points out all dma slave channels.
+ * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
+ * Select all channels from A to B, end of list is marked with -1,-1
+ */
+static int dma_slave_channels[] = {
+       U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
+       U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
+
+/* points out all dma memcpy channels. */
+static int dma_memcpy_channels[] = {
+       U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
+
+/** register dma for memory access
+ *
+ * active  1 means dma intends to access memory
+ *         0 means dma wont access memory
+ */
+static void coh901318_access_memory_state(struct device *dev, bool active)
+{
+}
+
+#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
+                       COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
+                       COH901318_CX_CFG_LCR_DISABLE | \
+                       COH901318_CX_CFG_TC_IRQ_ENABLE | \
+                       COH901318_CX_CFG_BE_IRQ_ENABLE)
+#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
+                       COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
+                       COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
+                       COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
+                       COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
+                       COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
+                       COH901318_CX_CTRL_MASTER_MODE_M1RW | \
+                       COH901318_CX_CTRL_TCP_DISABLE | \
+                       COH901318_CX_CTRL_TC_IRQ_DISABLE | \
+                       COH901318_CX_CTRL_HSP_DISABLE | \
+                       COH901318_CX_CTRL_HSS_DISABLE | \
+                       COH901318_CX_CTRL_DDMA_LEGACY | \
+                       COH901318_CX_CTRL_PRDD_SOURCE)
+#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
+                       COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
+                       COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
+                       COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
+                       COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
+                       COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
+                       COH901318_CX_CTRL_MASTER_MODE_M1RW | \
+                       COH901318_CX_CTRL_TCP_DISABLE | \
+                       COH901318_CX_CTRL_TC_IRQ_DISABLE | \
+                       COH901318_CX_CTRL_HSP_DISABLE | \
+                       COH901318_CX_CTRL_HSS_DISABLE | \
+                       COH901318_CX_CTRL_DDMA_LEGACY | \
+                       COH901318_CX_CTRL_PRDD_SOURCE)
+#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
+                       COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
+                       COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
+                       COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
+                       COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
+                       COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
+                       COH901318_CX_CTRL_MASTER_MODE_M1RW | \
+                       COH901318_CX_CTRL_TCP_DISABLE | \
+                       COH901318_CX_CTRL_TC_IRQ_ENABLE | \
+                       COH901318_CX_CTRL_HSP_DISABLE | \
+                       COH901318_CX_CTRL_HSS_DISABLE | \
+                       COH901318_CX_CTRL_DDMA_LEGACY | \
+                       COH901318_CX_CTRL_PRDD_SOURCE)
+
+const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
+       {
+               .number = U300_DMA_MSL_TX_0,
+               .name = "MSL TX 0",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
+       },
+       {
+               .number = U300_DMA_MSL_TX_1,
+               .name = "MSL TX 1",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+       },
+       {
+               .number = U300_DMA_MSL_TX_2,
+               .name = "MSL TX 2",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .desc_nbr_max = 10,
+       },
+       {
+               .number = U300_DMA_MSL_TX_3,
+               .name = "MSL TX 3",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+       },
+       {
+               .number = U300_DMA_MSL_TX_4,
+               .name = "MSL TX 4",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+       },
+       {
+               .number = U300_DMA_MSL_TX_5,
+               .name = "MSL TX 5",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
+       },
+       {
+               .number = U300_DMA_MSL_TX_6,
+               .name = "MSL TX 6",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
+       },
+       {
+               .number = U300_DMA_MSL_RX_0,
+               .name = "MSL RX 0",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
+       },
+       {
+               .number = U300_DMA_MSL_RX_1,
+               .name = "MSL RX 1",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli = 0,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+       },
+       {
+               .number = U300_DMA_MSL_RX_2,
+               .name = "MSL RX 2",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+       },
+       {
+               .number = U300_DMA_MSL_RX_3,
+               .name = "MSL RX 3",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+       },
+       {
+               .number = U300_DMA_MSL_RX_4,
+               .name = "MSL RX 4",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+       },
+       {
+               .number = U300_DMA_MSL_RX_5,
+               .name = "MSL RX 5",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+       },
+       {
+               .number = U300_DMA_MSL_RX_6,
+               .name = "MSL RX 6",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
+       },
+       /*
+        * Don't set up device address, burst count or size of src
+        * or dst bus for this peripheral - handled by PrimeCell
+        * DMA extension.
+        */
+       {
+               .number = U300_DMA_MMCSD_RX_TX,
+               .name = "MMCSD RX TX",
+               .priority_high = 0,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY,
+
+       },
+       {
+               .number = U300_DMA_MSPRO_TX,
+               .name = "MSPRO TX",
+               .priority_high = 0,
+       },
+       {
+               .number = U300_DMA_MSPRO_RX,
+               .name = "MSPRO RX",
+               .priority_high = 0,
+       },
+       /*
+        * Don't set up device address, burst count or size of src
+        * or dst bus for this peripheral - handled by PrimeCell
+        * DMA extension.
+        */
+       {
+               .number = U300_DMA_UART0_TX,
+               .name = "UART0 TX",
+               .priority_high = 0,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY,
+       },
+       {
+               .number = U300_DMA_UART0_RX,
+               .name = "UART0 RX",
+               .priority_high = 0,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY,
+       },
+       {
+               .number = U300_DMA_APEX_TX,
+               .name = "APEX TX",
+               .priority_high = 0,
+       },
+       {
+               .number = U300_DMA_APEX_RX,
+               .name = "APEX RX",
+               .priority_high = 0,
+       },
+       {
+               .number = U300_DMA_PCM_I2S0_TX,
+               .name = "PCM I2S0 TX",
+               .priority_high = 1,
+               .dev_addr = U300_PCM_I2S0_BASE + 0x14,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+       },
+       {
+               .number = U300_DMA_PCM_I2S0_RX,
+               .name = "PCM I2S0 RX",
+               .priority_high = 1,
+               .dev_addr = U300_PCM_I2S0_BASE + 0x10,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_DEST,
+       },
+       {
+               .number = U300_DMA_PCM_I2S1_TX,
+               .name = "PCM I2S1 TX",
+               .priority_high = 1,
+               .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+       },
+       {
+               .number = U300_DMA_PCM_I2S1_RX,
+               .name = "PCM I2S1 RX",
+               .priority_high = 1,
+               .dev_addr = U300_PCM_I2S1_BASE + 0x10,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_DEST,
+       },
+       {
+               .number = U300_DMA_XGAM_CDI,
+               .name = "XGAM CDI",
+               .priority_high = 0,
+       },
+       {
+               .number = U300_DMA_XGAM_PDI,
+               .name = "XGAM PDI",
+               .priority_high = 0,
+       },
+       /*
+        * Don't set up device address, burst count or size of src
+        * or dst bus for this peripheral - handled by PrimeCell
+        * DMA extension.
+        */
+       {
+               .number = U300_DMA_SPI_TX,
+               .name = "SPI TX",
+               .priority_high = 0,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY,
+       },
+       {
+               .number = U300_DMA_SPI_RX,
+               .name = "SPI RX",
+               .priority_high = 0,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY,
+
+       },
+       {
+               .number = U300_DMA_GENERAL_PURPOSE_0,
+               .name = "GENERAL 00",
+               .priority_high = 0,
+
+               .param.config = flags_memcpy_config,
+               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+               .param.ctrl_lli = flags_memcpy_lli,
+               .param.ctrl_lli_last = flags_memcpy_lli_last,
+       },
+       {
+               .number = U300_DMA_GENERAL_PURPOSE_1,
+               .name = "GENERAL 01",
+               .priority_high = 0,
+
+               .param.config = flags_memcpy_config,
+               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+               .param.ctrl_lli = flags_memcpy_lli,
+               .param.ctrl_lli_last = flags_memcpy_lli_last,
+       },
+       {
+               .number = U300_DMA_GENERAL_PURPOSE_2,
+               .name = "GENERAL 02",
+               .priority_high = 0,
+
+               .param.config = flags_memcpy_config,
+               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+               .param.ctrl_lli = flags_memcpy_lli,
+               .param.ctrl_lli_last = flags_memcpy_lli_last,
+       },
+       {
+               .number = U300_DMA_GENERAL_PURPOSE_3,
+               .name = "GENERAL 03",
+               .priority_high = 0,
+
+               .param.config = flags_memcpy_config,
+               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+               .param.ctrl_lli = flags_memcpy_lli,
+               .param.ctrl_lli_last = flags_memcpy_lli_last,
+       },
+       {
+               .number = U300_DMA_GENERAL_PURPOSE_4,
+               .name = "GENERAL 04",
+               .priority_high = 0,
+
+               .param.config = flags_memcpy_config,
+               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+               .param.ctrl_lli = flags_memcpy_lli,
+               .param.ctrl_lli_last = flags_memcpy_lli_last,
+       },
+       {
+               .number = U300_DMA_GENERAL_PURPOSE_5,
+               .name = "GENERAL 05",
+               .priority_high = 0,
+
+               .param.config = flags_memcpy_config,
+               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+               .param.ctrl_lli = flags_memcpy_lli,
+               .param.ctrl_lli_last = flags_memcpy_lli_last,
+       },
+       {
+               .number = U300_DMA_GENERAL_PURPOSE_6,
+               .name = "GENERAL 06",
+               .priority_high = 0,
+
+               .param.config = flags_memcpy_config,
+               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+               .param.ctrl_lli = flags_memcpy_lli,
+               .param.ctrl_lli_last = flags_memcpy_lli_last,
+       },
+       {
+               .number = U300_DMA_GENERAL_PURPOSE_7,
+               .name = "GENERAL 07",
+               .priority_high = 0,
+
+               .param.config = flags_memcpy_config,
+               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+               .param.ctrl_lli = flags_memcpy_lli,
+               .param.ctrl_lli_last = flags_memcpy_lli_last,
+       },
+       {
+               .number = U300_DMA_GENERAL_PURPOSE_8,
+               .name = "GENERAL 08",
+               .priority_high = 0,
+
+               .param.config = flags_memcpy_config,
+               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+               .param.ctrl_lli = flags_memcpy_lli,
+               .param.ctrl_lli_last = flags_memcpy_lli_last,
+       },
+       {
+               .number = U300_DMA_UART1_TX,
+               .name = "UART1 TX",
+               .priority_high = 0,
+       },
+       {
+               .number = U300_DMA_UART1_RX,
+               .name = "UART1 RX",
+               .priority_high = 0,
+       }
+};
+
+static struct coh901318_platform coh901318_platform = {
+       .chans_slave = dma_slave_channels,
+       .chans_memcpy = dma_memcpy_channels,
+       .access_memory_state = coh901318_access_memory_state,
+       .chan_conf = chan_config,
+       .max_channels = U300_DMA_CHANNELS,
+};
+
 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
 
 #ifdef VERBOSE_DEBUG
@@ -1448,9 +2532,7 @@ static int __init coh901318_probe(struct platform_device *pdev)
                                    pdev->dev.driver->name) == NULL)
                return -ENOMEM;
 
-       pdata = pdev->dev.platform_data;
-       if (!pdata)
-               return -ENODEV;
+       pdata = &coh901318_platform,
 
        base = devm_kzalloc(&pdev->dev,
                            ALIGN(sizeof(struct coh901318_base), 4) +