[media] saa7115: add support for double-rate ASCLK

Some devices expect a double rate ASCLK. Add a flag to let the driver know
through the s_crystal_freq call.

Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

diff --git a/drivers/media/i2c/saa7115.c b/drivers/media/i2c/saa7115.c
index cdff1f6e8546018c4b123d71990c35459f436adb..52c717d977c937aff0e39c7194bf9089f0648c19 100644 (file)
--- a/drivers/media/i2c/saa7115.c
+++ b/drivers/media/i2c/saa7115.c
@@ -83,9 +83,10 @@ struct saa711x_state {
        u32 ident;
        u32 audclk_freq;
        u32 crystal_freq;
-       u8 ucgc;
+       bool ucgc;
        u8 cgcdiv;
-       u8 apll;
+       bool apll;
+       bool double_asclk;
 };
 
 static inline struct saa711x_state *to_state(struct v4l2_subdev *sd)
@@ -732,8 +733,12 @@ static int saa711x_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
        if (state->apll)
                acc |= 0x08;
 
+       if (state->double_asclk) {
+               acpf <<= 1;
+               acni <<= 1;
+       }
        saa711x_write(sd, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03);
-       saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10);
+       saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10 << state->double_asclk);
        saa711x_write(sd, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc);
 
        saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff);
@@ -1302,9 +1307,10 @@ static int saa711x_s_crystal_freq(struct v4l2_subdev *sd, u32 freq, u32 flags)
        if (freq != SAA7115_FREQ_32_11_MHZ && freq != SAA7115_FREQ_24_576_MHZ)
                return -EINVAL;
        state->crystal_freq = freq;
+       state->double_asclk = flags & SAA7115_FREQ_FL_DOUBLE_ASCLK;
        state->cgcdiv = (flags & SAA7115_FREQ_FL_CGCDIV) ? 3 : 4;
-       state->ucgc = (flags & SAA7115_FREQ_FL_UCGC) ? 1 : 0;
-       state->apll = (flags & SAA7115_FREQ_FL_APLL) ? 1 : 0;
+       state->ucgc = flags & SAA7115_FREQ_FL_UCGC;
+       state->apll = flags & SAA7115_FREQ_FL_APLL;
        saa711x_s_clock_freq(sd, state->audclk_freq);
        return 0;
 }

diff --git a/include/media/saa7115.h b/include/media/saa7115.h
index 8b2ecc69a7029c3be2533617192ffaa479552f04..407918625c804cc3fa6ab33e8b53b722b1e07248 100644 (file)
--- a/include/media/saa7115.h
+++ b/include/media/saa7115.h
@@ -59,9 +59,10 @@
 #define SAA7115_FREQ_24_576_MHZ 24576000   /* 24.576 MHz crystal */
 
 /* SAA7115 v4l2_crystal_freq audio clock control flags */
-#define SAA7115_FREQ_FL_UCGC   (1 << 0)           /* SA 3A[7], UCGC, SAA7115 only */
-#define SAA7115_FREQ_FL_CGCDIV (1 << 1)           /* SA 3A[6], CGCDIV, SAA7115 only */
-#define SAA7115_FREQ_FL_APLL   (1 << 2)           /* SA 3A[3], APLL, SAA7114/5 only */
+#define SAA7115_FREQ_FL_UCGC         (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */
+#define SAA7115_FREQ_FL_CGCDIV       (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */
+#define SAA7115_FREQ_FL_APLL         (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */
+#define SAA7115_FREQ_FL_DOUBLE_ASCLK (1 << 3) /* SA 39, LRDIV, SAA7114/5 only */
 
 #endif