drm/i915: Flush using only the correct base address register

We were writing DSP_ADDR and DSP_SURF unconditionally. This did not
trigger an unclaimed write before HSW as the address of DSP_ADDR has
been repurposed as DSP_LINOFF.

On HSW, though, DSP_LINOFF has been removed and then writting to it
triggers an unclaimed write.

This patch writes to DSP_ADDR or DSP_SURF to flush the display plane
configuration depending on the gen we're running on.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1096066cd2ebc5c28dc4887389c5ae584e51d30c..fe2bb77c221d33acae63d69707ad74b7796cc4b6 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1836,8 +1836,10 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
                                      enum plane plane)
 {
-       I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
-       I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
+       if (dev_priv->info->gen >= 4)
+               I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
+       else
+               I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
 }
 
 /**