]> Pileus Git - ~andy/linux/commitdiff
Provide functions to access cop0 config4-7 registers
authorRalf Baechle <ralf@linux-mips.org>
Sun, 6 Feb 2005 21:24:55 +0000 (21:24 +0000)
committerRalf Baechle <ralf@linux-mips.org>
Sat, 29 Oct 2005 18:30:25 +0000 (19:30 +0100)
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
include/asm-mips/mipsregs.h

index 2197aa4ce4560a85661307722584f9aa9c3d0174..006354ed2e296cfdf14507698cd2c26e53a12ffe 100644 (file)
@@ -790,10 +790,18 @@ do {                                                                      \
 #define read_c0_config1()      __read_32bit_c0_register($16, 1)
 #define read_c0_config2()      __read_32bit_c0_register($16, 2)
 #define read_c0_config3()      __read_32bit_c0_register($16, 3)
+#define read_c0_config4()      __read_32bit_c0_register($16, 4)
+#define read_c0_config5()      __read_32bit_c0_register($16, 5)
+#define read_c0_config6()      __read_32bit_c0_register($16, 6)
+#define read_c0_config7()      __read_32bit_c0_register($16, 7)
 #define write_c0_config(val)   __write_32bit_c0_register($16, 0, val)
 #define write_c0_config1(val)  __write_32bit_c0_register($16, 1, val)
 #define write_c0_config2(val)  __write_32bit_c0_register($16, 2, val)
 #define write_c0_config3(val)  __write_32bit_c0_register($16, 3, val)
+#define write_c0_config4(val)  __write_32bit_c0_register($16, 4, val)
+#define write_c0_config5(val)  __write_32bit_c0_register($16, 5, val)
+#define write_c0_config6(val)  __write_32bit_c0_register($16, 6, val)
+#define write_c0_config7(val)  __write_32bit_c0_register($16, 7, val)
 
 /*
  * The WatchLo register.  There may be upto 8 of them.