+ return pll_rate / 4;
+
+ return pll_rate / 3;
+}
+
+static __init unsigned long
+mt7620_get_sys_rate(unsigned long cpu_rate)
+{
+ u32 reg;
+ u32 ocp_ratio;
+ u32 div;
+
+ reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
+
+ ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
+ CPU_SYS_CLKCFG_OCP_RATIO_MASK;
+
+ if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
+ return cpu_rate;
+
+ div = mt7620_ocp_dividers[ocp_ratio];
+ if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
+ return cpu_rate;
+
+ return cpu_rate / div;
+}
+
+void __init ralink_clk_init(void)
+{
+ unsigned long xtal_rate;
+ unsigned long cpu_pll_rate;
+ unsigned long pll_rate;
+ unsigned long cpu_rate;
+ unsigned long sys_rate;
+ unsigned long dram_rate;
+ unsigned long periph_rate;
+
+ xtal_rate = mt7620_get_xtal_rate();
+
+ cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
+ pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
+
+ cpu_rate = mt7620_get_cpu_rate(pll_rate);
+ dram_rate = mt7620_get_dram_rate(pll_rate);
+ sys_rate = mt7620_get_sys_rate(cpu_rate);
+ periph_rate = mt7620_get_periph_rate(xtal_rate);
+
+#define RFMT(label) label ":%lu.%03luMHz "
+#define RINT(x) ((x) / 1000000)
+#define RFRAC(x) (((x) / 1000) % 1000)
+
+ pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
+ RINT(xtal_rate), RFRAC(xtal_rate),
+ RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
+ RINT(pll_rate), RFRAC(pll_rate));
+
+ pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
+ RINT(cpu_rate), RFRAC(cpu_rate),
+ RINT(dram_rate), RFRAC(dram_rate),
+ RINT(sys_rate), RFRAC(sys_rate),
+ RINT(periph_rate), RFRAC(periph_rate));
+
+#undef RFRAC
+#undef RINT
+#undef RFMT