I've maintained this patch, originally from Thiemo Seufer in 2004, for a
really long time, but I think it's time for it to get a look at for
possible inclusion. I have had no problems with it across various SGI
systems over the years.
To quote the post here:
http://www.linux-mips.org/archives/linux-mips/2004-12/msg00000.html
"the atomic functions use so far memory references for the inline
assembler to access the semaphore. This can lead to additional
instructions in the ll/sc loop, because newer compilers don't
expand the memory reference any more but leave it to the assembler.
The appended patch uses registers instead, and makes the ll/sc
arguments more explicit. In some cases it will lead also to better
register scheduling because the register isn't bound to an output
any more."
Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4029/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
" sc %0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
" sc %0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ : "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else if (kernel_uses_llsc) {
int temp;
} else if (kernel_uses_llsc) {
int temp;
" addu %0, %2 \n"
" sc %0, %1 \n"
" .set mips0 \n"
" addu %0, %2 \n"
" sc %0, %1 \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ : "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} while (unlikely(!temp));
} else {
unsigned long flags;
} while (unlikely(!temp));
} else {
unsigned long flags;
" sc %0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
" sc %0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ : "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else if (kernel_uses_llsc) {
int temp;
} else if (kernel_uses_llsc) {
int temp;
" subu %0, %2 \n"
" sc %0, %1 \n"
" .set mips0 \n"
" subu %0, %2 \n"
" sc %0, %1 \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ : "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} while (unlikely(!temp));
} else {
unsigned long flags;
} while (unlikely(!temp));
} else {
unsigned long flags;
" beqzl %0, 1b \n"
" addu %0, %1, %3 \n"
" .set mips0 \n"
" beqzl %0, 1b \n"
" addu %0, %1, %3 \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else if (kernel_uses_llsc) {
int temp;
} else if (kernel_uses_llsc) {
int temp;
" addu %0, %1, %3 \n"
" sc %0, %2 \n"
" .set mips0 \n"
" addu %0, %1, %3 \n"
" sc %0, %2 \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} while (unlikely(!result));
result = temp + i;
} while (unlikely(!result));
result = temp + i;
" subu %0, %1, %3 \n"
" sc %0, %2 \n"
" .set mips0 \n"
" subu %0, %1, %3 \n"
" sc %0, %2 \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} while (unlikely(!result));
result = temp - i;
} while (unlikely(!result));
result = temp - i;
" .set reorder \n"
"1: \n"
" .set mips0 \n"
" .set reorder \n"
"1: \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (kernel_uses_llsc) {
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (kernel_uses_llsc) {
" .set reorder \n"
"1: \n"
" .set mips0 \n"
" .set reorder \n"
"1: \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else {
unsigned long flags;
} else {
unsigned long flags;
" scd %0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
" scd %0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ : "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else if (kernel_uses_llsc) {
long temp;
} else if (kernel_uses_llsc) {
long temp;
" daddu %0, %2 \n"
" scd %0, %1 \n"
" .set mips0 \n"
" daddu %0, %2 \n"
" scd %0, %1 \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ : "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} while (unlikely(!temp));
} else {
unsigned long flags;
} while (unlikely(!temp));
} else {
unsigned long flags;
" scd %0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
" scd %0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ : "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else if (kernel_uses_llsc) {
long temp;
} else if (kernel_uses_llsc) {
long temp;
" dsubu %0, %2 \n"
" scd %0, %1 \n"
" .set mips0 \n"
" dsubu %0, %2 \n"
" scd %0, %1 \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ : "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} while (unlikely(!temp));
} else {
unsigned long flags;
} while (unlikely(!temp));
} else {
unsigned long flags;
" beqzl %0, 1b \n"
" daddu %0, %1, %3 \n"
" .set mips0 \n"
" beqzl %0, 1b \n"
" daddu %0, %1, %3 \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else if (kernel_uses_llsc) {
long temp;
} else if (kernel_uses_llsc) {
long temp;
" .set reorder \n"
"1: \n"
" .set mips0 \n"
" .set reorder \n"
"1: \n"
" .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+ : "Ir" (i));
} else {
unsigned long flags;
} else {
unsigned long flags;