Fix following Section mismatch warning in sparc64:
WARNING: arch/sparc64/kernel/built-in.o(.text+0x13dec): Section mismatch: reference to .devinit.text:pci_scan_one_pbm (between 'psycho_scan_bus' and 'psycho_pbm_init')
WARNING: arch/sparc64/kernel/built-in.o(.text+0x14b58): Section mismatch: reference to .devinit.text:pci_scan_one_pbm (between 'sabre_scan_bus' and 'sabre_init')
WARNING: arch/sparc64/kernel/built-in.o(.text+0x15ea4): Section mismatch: reference to .devinit.text:pci_scan_one_pbm (between 'schizo_scan_bus' and 'schizo_pbm_init')
WARNING: arch/sparc64/kernel/built-in.o(.text+0x17780): Section mismatch: reference to .devinit.text:pci_scan_one_pbm (between 'pci_sun4v_scan_bus' and 'pci_sun4v_get_head')
WARNING: arch/sparc64/kernel/built-in.o(.text+0x17d5c): Section mismatch: reference to .devinit.text:pci_scan_one_pbm (between 'pci_fire_scan_bus' and 'pci_fire_get_head')
WARNING: arch/sparc64/kernel/built-in.o(.text+0x23860): Section mismatch: reference to .devinit.text:vio_dev_release (between 'vio_create_one' and 'vio_add')
WARNING: arch/sparc64/kernel/built-in.o(.text+0x23868): Section mismatch: reference to .devinit.text:vio_dev_release (between 'vio_create_one' and 'vio_add')
The pci_* were all missing __init annotations.
For the vio.c case it was a function with a wrong annotation which was removed.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
"i" (ASI_PHYS_BYPASS_EC_E) \
: "memory")
"i" (ASI_PHYS_BYPASS_EC_E) \
: "memory")
-static void pci_fire_scan_bus(struct pci_pbm_info *pbm)
+static void __init pci_fire_scan_bus(struct pci_pbm_info *pbm)
{
pbm->pci_bus = pci_scan_one_pbm(pbm);
{
pbm->pci_bus = pci_scan_one_pbm(pbm);
fire_write(pbm->pbm_regs + FIRE_PEC_IENAB, ~(u64)0);
}
fire_write(pbm->pbm_regs + FIRE_PEC_IENAB, ~(u64)0);
}
-static int pci_fire_pbm_init(struct pci_controller_info *p,
- struct device_node *dp, u32 portid)
+static int __init pci_fire_pbm_init(struct pci_controller_info *p,
+ struct device_node *dp, u32 portid)
{
const struct linux_prom64_registers *regs;
struct pci_pbm_info *pbm;
{
const struct linux_prom64_registers *regs;
struct pci_pbm_info *pbm;
-void fire_pci_init(struct device_node *dp, const char *model_name)
+void __init fire_pci_init(struct device_node *dp, const char *model_name)
{
struct pci_controller_info *p;
u32 portid = of_getintprop_default(dp, "portid", 0xff);
{
struct pci_controller_info *p;
u32 portid = of_getintprop_default(dp, "portid", 0xff);
pci_config_write8(addr, 64);
}
pci_config_write8(addr, 64);
}
-static void psycho_scan_bus(struct pci_pbm_info *pbm)
+static void __init psycho_scan_bus(struct pci_pbm_info *pbm)
{
pbm_config_busmastering(pbm);
pbm->is_66mhz_capable = 0;
{
pbm_config_busmastering(pbm);
pbm->is_66mhz_capable = 0;
#define PSYCHO_MEMSPACE_B 0x180000000UL
#define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
#define PSYCHO_MEMSPACE_B 0x180000000UL
#define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
-static void psycho_pbm_init(struct pci_controller_info *p,
+static void __init psycho_pbm_init(struct pci_controller_info *p,
struct device_node *dp, int is_pbm_a)
{
struct property *prop;
struct device_node *dp, int is_pbm_a)
{
struct property *prop;
#define PSYCHO_CONFIGSPACE 0x001000000UL
#define PSYCHO_CONFIGSPACE 0x001000000UL
-void psycho_init(struct device_node *dp, char *model_name)
+void __init psycho_init(struct device_node *dp, char *model_name)
{
struct linux_prom64_registers *pr_regs;
struct pci_controller_info *p;
{
struct linux_prom64_registers *pr_regs;
struct pci_controller_info *p;
-static void sabre_scan_bus(struct pci_pbm_info *pbm)
+static void __init sabre_scan_bus(struct pci_pbm_info *pbm)
-static void sabre_pbm_init(struct pci_controller_info *p, struct pci_pbm_info *pbm, struct device_node *dp)
+static void __init sabre_pbm_init(struct pci_controller_info *p,
+ struct pci_pbm_info *pbm, struct device_node *dp)
{
pbm->name = dp->full_name;
printk("%s: SABRE PCI Bus Module\n", pbm->name);
{
pbm->name = dp->full_name;
printk("%s: SABRE PCI Bus Module\n", pbm->name);
pci_determine_mem_io_space(pbm);
}
pci_determine_mem_io_space(pbm);
}
-void sabre_init(struct device_node *dp, char *model_name)
+void __init sabre_init(struct device_node *dp, char *model_name)
{
const struct linux_prom64_registers *pr_regs;
struct pci_controller_info *p;
{
const struct linux_prom64_registers *pr_regs;
struct pci_controller_info *p;
pci_config_write8(addr, 64);
}
pci_config_write8(addr, 64);
}
-static void schizo_scan_bus(struct pci_pbm_info *pbm)
+static void __init schizo_scan_bus(struct pci_pbm_info *pbm)
{
pbm_config_busmastering(pbm);
pbm->is_66mhz_capable =
{
pbm_config_busmastering(pbm);
pbm->is_66mhz_capable =
-static int schizo_pbm_init(struct pci_controller_info *p,
- struct device_node *dp, u32 portid,
- int chip_type)
+static int __init schizo_pbm_init(struct pci_controller_info *p,
+ struct device_node *dp, u32 portid,
+ int chip_type)
{
const struct linux_prom64_registers *regs;
struct pci_pbm_info *pbm;
{
const struct linux_prom64_registers *regs;
struct pci_pbm_info *pbm;
-static void __schizo_init(struct device_node *dp, char *model_name, int chip_type)
+static void __init __schizo_init(struct device_node *dp, char *model_name,
+ int chip_type)
{
struct pci_controller_info *p;
struct pci_pbm_info *pbm;
{
struct pci_controller_info *p;
struct pci_pbm_info *pbm;
-void schizo_init(struct device_node *dp, char *model_name)
+void __init schizo_init(struct device_node *dp, char *model_name)
{
__schizo_init(dp, model_name, PBM_CHIP_TYPE_SCHIZO);
}
{
__schizo_init(dp, model_name, PBM_CHIP_TYPE_SCHIZO);
}
-void schizo_plus_init(struct device_node *dp, char *model_name)
+void __init schizo_plus_init(struct device_node *dp, char *model_name)
{
__schizo_init(dp, model_name, PBM_CHIP_TYPE_SCHIZO_PLUS);
}
{
__schizo_init(dp, model_name, PBM_CHIP_TYPE_SCHIZO_PLUS);
}
-void tomatillo_init(struct device_node *dp, char *model_name)
+void __init tomatillo_init(struct device_node *dp, char *model_name)
{
__schizo_init(dp, model_name, PBM_CHIP_TYPE_TOMATILLO);
}
{
__schizo_init(dp, model_name, PBM_CHIP_TYPE_TOMATILLO);
}
.sync_sg_for_cpu = dma_4v_sync_sg_for_cpu,
};
.sync_sg_for_cpu = dma_4v_sync_sg_for_cpu,
};
-static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm)
+static void __init pci_sun4v_scan_bus(struct pci_pbm_info *pbm)
{
struct property *prop;
struct device_node *dp;
{
struct property *prop;
struct device_node *dp;
}
#endif /* !(CONFIG_PCI_MSI) */
}
#endif /* !(CONFIG_PCI_MSI) */
-static void __init pci_sun4v_pbm_init(struct pci_controller_info *p, struct device_node *dp, u32 devhandle)
+static void __init pci_sun4v_pbm_init(struct pci_controller_info *p,
+ struct device_node *dp, u32 devhandle)
{
struct pci_pbm_info *pbm;
{
struct pci_pbm_info *pbm;
}
EXPORT_SYMBOL(vio_unregister_driver);
}
EXPORT_SYMBOL(vio_unregister_driver);
-static void __devinit vio_dev_release(struct device *dev)
+static void vio_dev_release(struct device *dev)
{
kfree(to_vio_dev(dev));
}
{
kfree(to_vio_dev(dev));
}