- if (D11REV_LT(wlc_hw->corerev, 11)) {
- /* if 32 bit writes are split into 16 bit writes, are they in the correct order
- * for our interface, low to high
- */
- reg16 = (volatile u16 *)®s->tsf_cfpstart;
-
- /* write the CFPStart register low half explicitly, starting a buffered write */
- W_REG(osh, reg16, 0xAAAA);
-
- /* Write a 32 bit value to CFPStart to test the 16 bit split order.
- * If the low 16 bits are written first, followed by the high 16 bits then the
- * 32 bit value 0xCCCCBBBB should end up in the register.
- * If the order is reversed, then the write to the high half will trigger a buffered
- * write of 0xCCCCAAAA.
- * If the bus is 32 bits, then this is not much of a test, and the reg should
- * have the correct value 0xCCCCBBBB.
- */
- W_REG(osh, ®s->tsf_cfpstart, 0xCCCCBBBB);
-
- /* verify with the 16 bit registers that have no side effects */
- val = R_REG(osh, ®s->tsf_cfpstrt_l);
- if (val != (uint) 0xBBBB) {
- WL_ERROR("wl%d: validate_chip_access: tsf_cfpstrt_l = 0x%x, expected 0x%x\n",
- wlc_hw->unit, val, 0xBBBB);
- return false;
- }
- val = R_REG(osh, ®s->tsf_cfpstrt_h);
- if (val != (uint) 0xCCCC) {
- WL_ERROR("wl%d: validate_chip_access: tsf_cfpstrt_h = 0x%x, expected 0x%x\n",
- wlc_hw->unit, val, 0xCCCC);
- return false;
- }
-
- }
-