]> Pileus Git - ~andy/linux/commit
drm/mgag200: Fix writes into MGA1064_PIX_CLK_CTL register
authorChristopher Harvey <charvey@matrox.com>
Fri, 12 Apr 2013 22:24:05 +0000 (22:24 +0000)
committerDave Airlie <airlied@redhat.com>
Mon, 13 May 2013 02:17:22 +0000 (12:17 +1000)
commitfb70a6690875315a3a1454e52fa339441ee7612b
tree21eddb213800b04e9b3a825a5158cb1c113ea3e8
parent9d8aa55ff6bd21f573581a29da32ad746f2edcfb
drm/mgag200: Fix writes into MGA1064_PIX_CLK_CTL register

The original line,
  WREG_DAC(MGA1064_PIX_CLK_CTL_CLK_DIS, tmp);
wrote tmp into MGA1064_PIX_CLK_CTL_CLK_DIS, where
MGA1064_PIX_CLK_CTL_CLK_DIS is an offset into
MGA1064_PIX_CLK_CTL. Change the line to write properly into
MGA1064_PIX_CLK_CTL. There were other chunks of code nearby that use
the same pattern (but work correctly), so this patch updates them all
to use this new (slightly more efficient) write pattern. The WREG_DAC
macro was causing the DAC_INDEX register to be set to the same value
twice. WREG8(DAC_DATA, foo) takes advantage of the fact that DAC_INDEX
is already at the value we want.

Signed-off-by: Christopher Harvey <charvey@matrox.com>
Acked-by: Julia Lemire <jlemire@matrox.com>
Tested-by: Julia Lemire <jlemire@matrox.com>
Acked-by: Mathieu Larouche <mathieu.larouche@matrox.com>
Cc: stable@vger.kernel.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/mgag200/mgag200_mode.c