]> Pileus Git - ~andy/linux/commit
MIPS: ralink: mt7620: Improve clock frequency detection
authorGabor Juhos <juhosg@openwrt.org>
Fri, 23 Aug 2013 06:31:30 +0000 (08:31 +0200)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 4 Sep 2013 14:57:05 +0000 (16:57 +0200)
commitded1e9d727f0e7cb1cf7f243dac2a87974ae048f
tree1b642fd72fda9849b8b48d03108eaf6019c4d0ab
parent2b9dbb15a9d4c7b8f87f98aa770f68fb60a7b170
MIPS: ralink: mt7620: Improve clock frequency detection

The current code assumes that the peripheral clock always
runs at 40MHz which is not true in all configuration. The
peripheral clock can also use the reference clock instead
of the fixed 40MHz rate. If the reference clock runs at a
different rate, various peripheries are behaving incorrectly.

Additionally, the currectly calculated system clock is also
wrong. The actual value what the code computes is the rate
of the DRAM which can be different from the system clock.

Add new helper functions to get the rate of the different
clocks and use the correct values for the registered clock
devices.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5755/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/mach-ralink/mt7620.h
arch/mips/ralink/mt7620.c