]> Pileus Git - ~andy/linux/commit
drm/i915: Prefer setting PTE cache age to 3
authorChris Wilson <chris@chris-wilson.co.uk>
Fri, 22 Nov 2013 10:37:53 +0000 (10:37 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 25 Nov 2013 08:50:15 +0000 (09:50 +0100)
commitc51e9701c4ad68d87baecefad6c58d051574f848
tree7e344de1371ff88e71b86a9e1ccf8eb121689058
parent76bb80ed3027fc51af24a378a5986672dc01398f
drm/i915: Prefer setting PTE cache age to 3

We have conflicting benchmark data that suggest either age 0 or age 3 is
better. However, the earlier benchmark on which we based the switch to
age 0

(commit 0d8ff15e9a15f2b393e53337a107b7a1e5919b6d
Author: Ben Widawsky <benjamin.widawsky@intel.com>
Date:   Thu Jul 4 11:02:03 2013 -0700

    drm/i915/hsw: Set correct Haswell PTE encodings)

actually seems to prefer the default PTE encoding as age 3. Presumably,
this is in part due to the use of MOCS to override the PTE encodings
when appropriate.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=69870
Tested-by: mengmeng.meng@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Eric Anholt <eric@anholt.net
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_gem_gtt.c