]> Pileus Git - ~andy/linux/commit
arm64: mm: Fix operands of clz in __flush_dcache_all
authorSukanto Ghosh <sghosh@apm.com>
Tue, 14 May 2013 09:26:54 +0000 (10:26 +0100)
committerCatalin Marinas <catalin.marinas@arm.com>
Tue, 14 May 2013 14:44:50 +0000 (15:44 +0100)
commitb4fed0796841b5293b9c9427a5391b7bb20ef2d9
tree0a17c86e49059cfbec754bc1664fdd2c1692ad50
parentc560ecfe9617c629ad09b07edb7523c87b2c9619
arm64: mm: Fix operands of clz in __flush_dcache_all

The format of the lower 32-bits of the 64-bit operand to 'dc cisw' is
unchanged from ARMv7 architecture and the upper bits are RES0. This
implies that the 'way' field of the operand of 'dc cisw' occupies the
bit-positions [31 .. (32-A)]. Due to the use of 64-bit extended operands
to 'clz', the existing implementation of __flush_dcache_all is incorrectly
placing the 'way' field in the bit-positions [63 .. (64-A)].

Signed-off-by: Sukanto Ghosh <sghosh@apm.com>
Tested-by: Anup Patel <anup.patel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: stable@vger.kernel.org
arch/arm64/mm/cache.S