]> Pileus Git - ~andy/linux/commit
drm/nv50/disp: use correct register to determine DP display bpp
authorIlia Mirkin <imirkin@alum.mit.edu>
Fri, 14 Feb 2014 02:57:15 +0000 (21:57 -0500)
committerBen Skeggs <bskeggs@redhat.com>
Tue, 18 Feb 2014 00:37:12 +0000 (10:37 +1000)
commita7f1c1e65b68e1e1ab70898528d5977ed68a0a7d
treedb506edec69abf4377820f75c4ba56509a533105
parent95ca5b550ac255bf3cee108c123407785c47e3cc
drm/nv50/disp: use correct register to determine DP display bpp

Commit 0a0afd282f ("drm/nv50-/disp: move DP link training to core and
train from supervisor") added code that uses the wrong register for
computing the display bpp, used for bandwidth calculation. Adjust to use
the same register as used by exec_clkcmp and nv50_disp_intr_unk20_2_dp.

Reported-by: Torsten Wagner <torsten.wagner@gmail.com>
Reported-by: Michael Gulick <mgulick@mathworks.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67628
Cc: stable@vger.kernel.org # 3.9+
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/core/engine/disp/nv50.c