]> Pileus Git - ~andy/linux/commit
drm/i915/bdw: Implement PPGTT enable
authorBen Widawsky <benjamin.widawsky@intel.com>
Tue, 5 Nov 2013 06:29:36 +0000 (22:29 -0800)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 8 Nov 2013 17:09:47 +0000 (18:09 +0100)
commit94e409c1449858b893c55d22f4e9ea9e845a91ed
tree5801fb8edaabd2974abcb2af36996599ed0905b2
parent9df15b499b083821b5e93fda8766b4e8eeabcd2b
drm/i915/bdw: Implement PPGTT enable

Legacy PPGTT on GEN8 requires programming 4 PDP registers per ring.
Since all rings are using the same address space with the current code
the logic is simply to program all the tables we've setup for the PPGTT.

v2: Turn on PPGTT in GFX_MODE

v3: v2 was the wrong patch

v4: Resolve conflicts due to patch series reordering.

v5: Squash in fixup from Ben: Use LRI to write PDPs

The docs (and simulator seems to back up) suggest that we can only
program legacy PPGTT PDPs with LRI commands.

v6: Rebase around context differences conflicts.

v7: Use #defines for per ring PDPs. (Damien)

v8: Don't use typede'f private_t.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (up to v3 and v7)
Reviewed-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_gem_gtt.c
drivers/gpu/drm/i915/i915_reg.h