]> Pileus Git - ~andy/linux/commit
powerpc/powernv: Reserve the correct PE number
authorGavin Shan <shangw@linux.vnet.ibm.com>
Mon, 4 Nov 2013 08:32:47 +0000 (16:32 +0800)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Wed, 6 Nov 2013 03:13:52 +0000 (14:13 +1100)
commit36954dc78d8a1dcd4780cf4bd0fc6292791821b9
tree896bea4d43edad65577bd4e061fa846bd57df786
parent631ad691b5818291d89af9be607d2fe40be0886e
powerpc/powernv: Reserve the correct PE number

We're assigning PE numbers after the completion of PCI probe. During
the PCI probe, we had PE#0 as the super container to encompass all
PCI devices. However, that's inappropriate since PELTM has ascending
order of priority on search on P7IOC. So we need PE#127 takes the
role that PE#0 has previously. For PHB3, we still have PE#0 as the
reserved PE.

The patch supposes that the underly firmware has built the RID to
PE# mapping after resetting IODA tables: all PELTM entries except
last one has invalid mapping on P7IOC, but all RTEs have binding
to PE#0. The reserved PE# is being exported by firmware by device
tree.

Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
arch/powerpc/platforms/powernv/pci-ioda.c
arch/powerpc/platforms/powernv/pci.c
arch/powerpc/platforms/powernv/pci.h