]> Pileus Git - ~andy/linux/commit
drm/i915: Fix pipe CSC post offset calculation
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 28 Nov 2013 20:10:38 +0000 (22:10 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 28 Nov 2013 21:47:41 +0000 (22:47 +0100)
commit32cf0cb0294814cb1ee5d8727e9aac0e9aa80d2e
tree287d2d26b1186c11fa52f3588cbb0bd9adf4040f
parent3b32a35b31b19c8f9340d3b3a149062fce1cd89f
drm/i915: Fix pipe CSC post offset calculation

We were miscalculating the pipe CSC post offset for the full->limited
range conversion. The resulting post offset was double what it was
supposed to be, which caused blacks to come out grey when using
limited range output on HSW+.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71769
Cc: stable@vger.kernel.org
Tested-by: Lauri Mylläri <lauri.myllari@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c