X-Git-Url: http://pileus.org/git/?a=blobdiff_plain;f=include%2Fasm-parisc%2Fspinlock.h;h=7c3f406a746a4f0984b07efc40e533b24d076561;hb=dad2ad82c5f058367df79de022bd12d36afcd065;hp=43eaa6e742e06f3a1f77dffca9d6eccf61fa29d4;hpb=fb1c8f93d869b34cacb8b8932e2b83d96a19d720;p=~andy%2Flinux

diff --git a/include/asm-parisc/spinlock.h b/include/asm-parisc/spinlock.h
index 43eaa6e742e..7c3f406a746 100644
--- a/include/asm-parisc/spinlock.h
+++ b/include/asm-parisc/spinlock.h
@@ -5,11 +5,6 @@
 #include <asm/processor.h>
 #include <asm/spinlock_types.h>
 
-/* Note that PA-RISC has to use `1' to mean unlocked and `0' to mean locked
- * since it only has load-and-zero. Moreover, at least on some PA processors,
- * the semaphore address has to be 16-byte aligned.
- */
-
 static inline int __raw_spin_is_locked(raw_spinlock_t *x)
 {
 	volatile unsigned int *a = __ldcw_align(x);