X-Git-Url: http://pileus.org/git/?a=blobdiff_plain;f=arch%2Fmips%2Fmm%2Ftlb-r4k.c;h=63065d6e806397202e93628db4dc0142e1ce642a;hb=afbf331ed1252c85753ac6790356c11e171f3d0b;hp=dcd6913dc1ff2696d64bb29198169af9ad86d1c1;hpb=b43035a5ec4deecd43019728ab9347df82dd121f;p=~andy%2Flinux diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index dcd6913dc1f..63065d6e806 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -388,7 +388,7 @@ void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, * lifetime of the system */ -static int temp_tlb_entry __initdata; +static int temp_tlb_entry __cpuinitdata; __init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask) @@ -427,7 +427,7 @@ out: return ret; } -static void __init probe_tlb(unsigned long config) +static void __cpuinit probe_tlb(unsigned long config) { struct cpuinfo_mips *c = ¤t_cpu_data; unsigned int reg; @@ -455,7 +455,7 @@ static void __init probe_tlb(unsigned long config) c->tlbsize = ((reg >> 25) & 0x3f) + 1; } -static int __initdata ntlb = 0; +static int __cpuinitdata ntlb = 0; static int __init set_ntlb(char *str) { get_option(&str, &ntlb); @@ -464,7 +464,7 @@ static int __init set_ntlb(char *str) __setup("ntlb=", set_ntlb); -void __init tlb_init(void) +void __cpuinit tlb_init(void) { unsigned int config = read_c0_config(); @@ -473,7 +473,7 @@ void __init tlb_init(void) * - On R4600 1.7 the tlbp never hits for pages smaller than * the value in the c0_pagemask register. * - The entire mm handling assumes the c0_pagemask register to - * be set for 4kb pages. + * be set to fixed-size pages. */ probe_tlb(config); write_c0_pagemask(PM_DEFAULT_MASK); @@ -491,7 +491,7 @@ void __init tlb_init(void) int wired = current_cpu_data.tlbsize - ntlb; write_c0_wired(wired); write_c0_index(wired-1); - printk ("Restricting TLB to %d entries\n", ntlb); + printk("Restricting TLB to %d entries\n", ntlb); } else printk("Ignoring invalid argument ntlb=%d\n", ntlb); }