X-Git-Url: http://pileus.org/git/?a=blobdiff_plain;f=arch%2Fmips%2Fkernel%2Fr4k_fpu.S;h=59c1577ecbb31e303dd8aa00d99d5dc3dfd4e13f;hb=37f26742437df885ddd72150ab352d0a931cd3a7;hp=880fa6e841ee95f678993fb5dd17138f62f5af22;hpb=c4e00fac42f268ed0a547cdd1d12bb8399864040;p=~andy%2Flinux

diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index 880fa6e841e..59c1577ecbb 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -114,6 +114,14 @@ LEAF(_save_fp_context32)
  */
 LEAF(_restore_fp_context)
 	EX	lw t0, SC_FPC_CSR(a0)
+
+	/* Fail if the CSR has exceptions pending */
+	srl	t1, t0, 5
+	and	t1, t0
+	andi	t1, 0x1f << 7
+	bnez	t1, fault
+	 nop
+
 #ifdef CONFIG_64BIT
 	EX	ldc1 $f1, SC_FPREGS+8(a0)
 	EX	ldc1 $f3, SC_FPREGS+24(a0)
@@ -157,6 +165,14 @@ LEAF(_restore_fp_context)
 LEAF(_restore_fp_context32)
 	/* Restore an o32 sigcontext.  */
 	EX	lw t0, SC32_FPC_CSR(a0)
+
+	/* Fail if the CSR has exceptions pending */
+	srl	t1, t0, 5
+	and	t1, t0
+	andi	t1, 0x1f << 7
+	bnez	t1, fault
+	 nop
+
 	EX	ldc1 $f0, SC32_FPREGS+0(a0)
 	EX	ldc1 $f2, SC32_FPREGS+16(a0)
 	EX	ldc1 $f4, SC32_FPREGS+32(a0)
@@ -177,9 +193,10 @@ LEAF(_restore_fp_context32)
 	jr	ra
 	 li	v0, 0					# success
 	END(_restore_fp_context32)
-	.set	reorder
 #endif
 
+	.set	reorder
+
 	.type	fault@function
 	.ent	fault
 fault:	li	v0, -EFAULT				# failure