X-Git-Url: http://pileus.org/git/?a=blobdiff_plain;f=arch%2Fmips%2Fcavium-octeon%2Fsetup.c;h=b212ae12e5ac7dc8ca35dfb24324ba638353f85e;hb=c224b76b560f3c65f0d10fbb59d3f00379eb0aaf;hp=48b08eb9d9e4bd29dc97f5ec97c3f763852ff4aa;hpb=3d7e5fc37f91c3ad4974262e173d9ba36139652a;p=~andy%2Flinux diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 48b08eb9d9e..b212ae12e5a 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -8,6 +8,7 @@ * written by Ralf Baechle */ #include +#include #include #include #include @@ -1139,3 +1140,30 @@ static int __init edac_devinit(void) return err; } device_initcall(edac_devinit); + +static void __initdata *octeon_dummy_iospace; + +static int __init octeon_no_pci_init(void) +{ + /* + * Initially assume there is no PCI. The PCI/PCIe platform code will + * later re-initialize these to correct values if they are present. + */ + octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT); + set_io_port_base((unsigned long)octeon_dummy_iospace); + ioport_resource.start = MAX_RESOURCE; + ioport_resource.end = 0; + return 0; +} +core_initcall(octeon_no_pci_init); + +static int __init octeon_no_pci_release(void) +{ + /* + * Release the allocated memory if a real IO space is there. + */ + if ((unsigned long)octeon_dummy_iospace != mips_io_port_base) + vfree(octeon_dummy_iospace); + return 0; +} +late_initcall(octeon_no_pci_release);