X-Git-Url: http://pileus.org/git/?a=blobdiff_plain;f=arch%2Farm%2FKconfig.debug;h=a03b5a7059e2d059a34d7655fc6be7fe57ba1676;hb=7b9b04fb728ec0b94464ed902f3395aa592c5bcf;hp=e561adc1db0c358a1fdb921c0106cea0b0d6b704;hpb=2c757fd5d1a92086f225a75a8fac7cab242d11b0;p=~andy%2Flinux diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index e561adc1db0..a03b5a7059e 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -209,6 +209,14 @@ choice Say Y here if you want kernel low-level debugging support on i.MX50 or i.MX53. + config DEBUG_IMX6Q_UART2 + bool "i.MX6Q Debug UART2" + depends on SOC_IMX6Q + help + Say Y here if you want kernel low-level debugging support + on i.MX6Q UART2. This is correct for e.g. the SabreLite + board. + config DEBUG_IMX6Q_UART4 bool "i.MX6Q Debug UART4" depends on SOC_IMX6Q @@ -302,6 +310,32 @@ choice The uncompressor code port configuration is now handled by CONFIG_S3C_LOWLEVEL_UART_PORT. + config DEBUG_VEXPRESS_UART0_DETECT + bool "Autodetect UART0 on Versatile Express Cortex-A core tiles" + depends on ARCH_VEXPRESS && CPU_CP15_MMU + help + This option enables a simple heuristic which tries to determine + the motherboard's memory map variant (original or RS1) and then + choose the relevant UART0 base address. + + Note that this will only work with standard A-class core tiles, + and may fail with non-standard SMM or custom software models. + + config DEBUG_VEXPRESS_UART0_CA9 + bool "Use PL011 UART0 at 0x10009000 (V2P-CA9 core tile)" + depends on ARCH_VEXPRESS + help + This option selects UART0 at 0x10009000. Except for custom models, + this applies only to the V2P-CA9 tile. + + config DEBUG_VEXPRESS_UART0_RS1 + bool "Use PL011 UART0 at 0x1c090000 (RS1 complaint tiles)" + depends on ARCH_VEXPRESS + help + This option selects UART0 at 0x1c090000. This applies to most + of the tiles using the RS1 memory map, including all new A-class + core tiles, FPGA-based SMMs and software models. + config DEBUG_LL_UART_NONE bool "No low-level debugging UART" help