Merge branch 'perf/core' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux...

[~andy/linux] / sound / soc / codecs / wm5100-tables.c

diff --git a/sound/soc/codecs/wm5100-tables.c b/sound/soc/codecs/wm5100-tables.c
index 9a18fae68204f790a19c75e7fc527e1b25d3a1f5..e167207a19cc357250fe65c5376b2248e6866d1e 100644 (file)
--- a/sound/soc/codecs/wm5100-tables.c
+++ b/sound/soc/codecs/wm5100-tables.c
@@ -32,7 +32,18 @@ bool wm5100_volatile_register(struct device *dev, unsigned int reg)
        case WM5100_MIC_DETECT_3:
                return 1;
        default:
-               return 0;
+               if ((reg >= WM5100_DSP1_PM_0 && reg <= WM5100_DSP1_PM_1535) ||
+                   (reg >= WM5100_DSP1_ZM_0 && reg <= WM5100_DSP1_ZM_2047) ||
+                   (reg >= WM5100_DSP1_DM_0 && reg <= WM5100_DSP1_DM_511) ||
+                   (reg >= WM5100_DSP2_PM_0 && reg <= WM5100_DSP2_PM_1535) ||
+                   (reg >= WM5100_DSP2_ZM_0 && reg <= WM5100_DSP2_ZM_2047) ||
+                   (reg >= WM5100_DSP2_DM_0 && reg <= WM5100_DSP2_DM_511) ||
+                   (reg >= WM5100_DSP3_PM_0 && reg <= WM5100_DSP3_PM_1535) ||
+                   (reg >= WM5100_DSP3_ZM_0 && reg <= WM5100_DSP3_ZM_2047) ||
+                   (reg >= WM5100_DSP3_DM_0 && reg <= WM5100_DSP3_DM_511))
+                       return 1;
+               else
+                       return 0;
        }
 }
 
@@ -697,9 +708,110 @@ bool wm5100_readable_register(struct device *dev, unsigned int reg)
        case WM5100_HPLPF3_2:
        case WM5100_HPLPF4_1:
        case WM5100_HPLPF4_2:
+       case WM5100_DSP1_CONTROL_1:
+       case WM5100_DSP1_CONTROL_2:
+       case WM5100_DSP1_CONTROL_3:
+       case WM5100_DSP1_CONTROL_4:
+       case WM5100_DSP1_CONTROL_5:
+       case WM5100_DSP1_CONTROL_6:
+       case WM5100_DSP1_CONTROL_7:
+       case WM5100_DSP1_CONTROL_8:
+       case WM5100_DSP1_CONTROL_9:
+       case WM5100_DSP1_CONTROL_10:
+       case WM5100_DSP1_CONTROL_11:
+       case WM5100_DSP1_CONTROL_12:
+       case WM5100_DSP1_CONTROL_13:
+       case WM5100_DSP1_CONTROL_14:
+       case WM5100_DSP1_CONTROL_15:
+       case WM5100_DSP1_CONTROL_16:
+       case WM5100_DSP1_CONTROL_17:
+       case WM5100_DSP1_CONTROL_18:
+       case WM5100_DSP1_CONTROL_19:
+       case WM5100_DSP1_CONTROL_20:
+       case WM5100_DSP1_CONTROL_21:
+       case WM5100_DSP1_CONTROL_22:
+       case WM5100_DSP1_CONTROL_23:
+       case WM5100_DSP1_CONTROL_24:
+       case WM5100_DSP1_CONTROL_25:
+       case WM5100_DSP1_CONTROL_26:
+       case WM5100_DSP1_CONTROL_27:
+       case WM5100_DSP1_CONTROL_28:
+       case WM5100_DSP1_CONTROL_29:
+       case WM5100_DSP1_CONTROL_30:
+       case WM5100_DSP2_CONTROL_1:
+       case WM5100_DSP2_CONTROL_2:
+       case WM5100_DSP2_CONTROL_3:
+       case WM5100_DSP2_CONTROL_4:
+       case WM5100_DSP2_CONTROL_5:
+       case WM5100_DSP2_CONTROL_6:
+       case WM5100_DSP2_CONTROL_7:
+       case WM5100_DSP2_CONTROL_8:
+       case WM5100_DSP2_CONTROL_9:
+       case WM5100_DSP2_CONTROL_10:
+       case WM5100_DSP2_CONTROL_11:
+       case WM5100_DSP2_CONTROL_12:
+       case WM5100_DSP2_CONTROL_13:
+       case WM5100_DSP2_CONTROL_14:
+       case WM5100_DSP2_CONTROL_15:
+       case WM5100_DSP2_CONTROL_16:
+       case WM5100_DSP2_CONTROL_17:
+       case WM5100_DSP2_CONTROL_18:
+       case WM5100_DSP2_CONTROL_19:
+       case WM5100_DSP2_CONTROL_20:
+       case WM5100_DSP2_CONTROL_21:
+       case WM5100_DSP2_CONTROL_22:
+       case WM5100_DSP2_CONTROL_23:
+       case WM5100_DSP2_CONTROL_24:
+       case WM5100_DSP2_CONTROL_25:
+       case WM5100_DSP2_CONTROL_26:
+       case WM5100_DSP2_CONTROL_27:
+       case WM5100_DSP2_CONTROL_28:
+       case WM5100_DSP2_CONTROL_29:
+       case WM5100_DSP2_CONTROL_30:
+       case WM5100_DSP3_CONTROL_1:
+       case WM5100_DSP3_CONTROL_2:
+       case WM5100_DSP3_CONTROL_3:
+       case WM5100_DSP3_CONTROL_4:
+       case WM5100_DSP3_CONTROL_5:
+       case WM5100_DSP3_CONTROL_6:
+       case WM5100_DSP3_CONTROL_7:
+       case WM5100_DSP3_CONTROL_8:
+       case WM5100_DSP3_CONTROL_9:
+       case WM5100_DSP3_CONTROL_10:
+       case WM5100_DSP3_CONTROL_11:
+       case WM5100_DSP3_CONTROL_12:
+       case WM5100_DSP3_CONTROL_13:
+       case WM5100_DSP3_CONTROL_14:
+       case WM5100_DSP3_CONTROL_15:
+       case WM5100_DSP3_CONTROL_16:
+       case WM5100_DSP3_CONTROL_17:
+       case WM5100_DSP3_CONTROL_18:
+       case WM5100_DSP3_CONTROL_19:
+       case WM5100_DSP3_CONTROL_20:
+       case WM5100_DSP3_CONTROL_21:
+       case WM5100_DSP3_CONTROL_22:
+       case WM5100_DSP3_CONTROL_23:
+       case WM5100_DSP3_CONTROL_24:
+       case WM5100_DSP3_CONTROL_25:
+       case WM5100_DSP3_CONTROL_26:
+       case WM5100_DSP3_CONTROL_27:
+       case WM5100_DSP3_CONTROL_28:
+       case WM5100_DSP3_CONTROL_29:
+       case WM5100_DSP3_CONTROL_30:
                return 1;
        default:
-               return 0;
+               if ((reg >= WM5100_DSP1_PM_0 && reg <= WM5100_DSP1_PM_1535) ||
+                   (reg >= WM5100_DSP1_ZM_0 && reg <= WM5100_DSP1_ZM_2047) ||
+                   (reg >= WM5100_DSP1_DM_0 && reg <= WM5100_DSP1_DM_511) ||
+                   (reg >= WM5100_DSP2_PM_0 && reg <= WM5100_DSP2_PM_1535) ||
+                   (reg >= WM5100_DSP2_ZM_0 && reg <= WM5100_DSP2_ZM_2047) ||
+                   (reg >= WM5100_DSP2_DM_0 && reg <= WM5100_DSP2_DM_511) ||
+                   (reg >= WM5100_DSP3_PM_0 && reg <= WM5100_DSP3_PM_1535) ||
+                   (reg >= WM5100_DSP3_ZM_0 && reg <= WM5100_DSP3_ZM_2047) ||
+                   (reg >= WM5100_DSP3_DM_0 && reg <= WM5100_DSP3_DM_511))
+                       return 1;
+               else
+                       return 0;
        }
 }
 
@@ -1361,4 +1473,13 @@ struct reg_default wm5100_reg_defaults[WM5100_REGISTER_COUNT] = {
        { 0x0EC9, 0x0000 },  /* R3785  - HPLPF3_2 */
        { 0x0ECC, 0x0000 },  /* R3788  - HPLPF4_1 */
        { 0x0ECD, 0x0000 },  /* R3789  - HPLPF4_2 */
+       { 0x0F02, 0x0000 },  /* R3842  - DSP1 Control 2 */
+       { 0x0F03, 0x0000 },  /* R3843  - DSP1 Control 3 */
+       { 0x0F04, 0x0000 },  /* R3844  - DSP1 Control 4 */
+       { 0x1002, 0x0000 },  /* R4098  - DSP2 Control 2 */
+       { 0x1003, 0x0000 },  /* R4099  - DSP2 Control 3 */
+       { 0x1004, 0x0000 },  /* R4100  - DSP2 Control 4 */
+       { 0x1102, 0x0000 },  /* R4354  - DSP3 Control 2 */
+       { 0x1103, 0x0000 },  /* R4355  - DSP3 Control 3 */
+       { 0x1104, 0x0000 },  /* R4356  - DSP3 Control 4 */
 };