pwm: Use pr_* functions in pwm-samsung.c file

[~andy/linux] / include / drm / exynos_drm.h

diff --git a/include/drm/exynos_drm.h b/include/drm/exynos_drm.h
index e478de4e5d564e936302d753e65ac4e52768b3a7..68733587e700bb00b776114e4a19530425194143 100644 (file)
--- a/include/drm/exynos_drm.h
+++ b/include/drm/exynos_drm.h
@@ -29,6 +29,8 @@
 #ifndef _EXYNOS_DRM_H_
 #define _EXYNOS_DRM_H_
 
+#include "drm.h"
+
 /**
  * User-desired buffer creation information structure.
  *
@@ -62,6 +64,7 @@ struct drm_exynos_gem_map_off {
  * A structure for mapping buffer.
  *
  * @handle: a handle to gem object created.
+ * @pad: just padding to be 64-bit aligned.
  * @size: memory size to be mapped.
  * @mapped: having user virtual address mmaped.
  *     - this variable would be filled by exynos gem module
@@ -70,10 +73,26 @@ struct drm_exynos_gem_map_off {
  */
 struct drm_exynos_gem_mmap {
        unsigned int handle;
-       unsigned int size;
+       unsigned int pad;
+       uint64_t size;
        uint64_t mapped;
 };
 
+/**
+ * A structure to gem information.
+ *
+ * @handle: a handle to gem object created.
+ * @flags: flag value including memory type and cache attribute and
+ *     this value would be set by driver.
+ * @size: size to memory region allocated by gem and this size would
+ *     be set by driver.
+ */
+struct drm_exynos_gem_info {
+       unsigned int handle;
+       unsigned int flags;
+       uint64_t size;
+};
+
 /**
  * A structure for user connection request of virtual display.
  *
@@ -95,18 +114,64 @@ struct drm_exynos_plane_set_zpos {
 
 /* memory type definitions. */
 enum e_drm_exynos_gem_mem_type {
+       /* Physically Continuous memory and used as default. */
+       EXYNOS_BO_CONTIG        = 0 << 0,
        /* Physically Non-Continuous memory. */
        EXYNOS_BO_NONCONTIG     = 1 << 0,
-       EXYNOS_BO_MASK          = EXYNOS_BO_NONCONTIG
+       /* non-cachable mapping and used as default. */
+       EXYNOS_BO_NONCACHABLE   = 0 << 1,
+       /* cachable mapping. */
+       EXYNOS_BO_CACHABLE      = 1 << 1,
+       /* write-combine mapping. */
+       EXYNOS_BO_WC            = 1 << 2,
+       EXYNOS_BO_MASK          = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
+                                       EXYNOS_BO_WC
+};
+
+struct drm_exynos_g2d_get_ver {
+       __u32   major;
+       __u32   minor;
+};
+
+struct drm_exynos_g2d_cmd {
+       __u32   offset;
+       __u32   data;
+};
+
+enum drm_exynos_g2d_event_type {
+       G2D_EVENT_NOT,
+       G2D_EVENT_NONSTOP,
+       G2D_EVENT_STOP,         /* not yet */
+};
+
+struct drm_exynos_g2d_set_cmdlist {
+       __u64                                   cmd;
+       __u64                                   cmd_gem;
+       __u32                                   cmd_nr;
+       __u32                                   cmd_gem_nr;
+
+       /* for g2d event */
+       __u64                                   event_type;
+       __u64                                   user_data;
+};
+
+struct drm_exynos_g2d_exec {
+       __u64                                   async;
 };
 
 #define DRM_EXYNOS_GEM_CREATE          0x00
 #define DRM_EXYNOS_GEM_MAP_OFFSET      0x01
 #define DRM_EXYNOS_GEM_MMAP            0x02
 /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
+#define DRM_EXYNOS_GEM_GET             0x04
 #define DRM_EXYNOS_PLANE_SET_ZPOS      0x06
 #define DRM_EXYNOS_VIDI_CONNECTION     0x07
 
+/* G2D */
+#define DRM_EXYNOS_G2D_GET_VER         0x20
+#define DRM_EXYNOS_G2D_SET_CMDLIST     0x21
+#define DRM_EXYNOS_G2D_EXEC            0x22
+
 #define DRM_IOCTL_EXYNOS_GEM_CREATE            DRM_IOWR(DRM_COMMAND_BASE + \
                DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
 
@@ -116,12 +181,34 @@ enum e_drm_exynos_gem_mem_type {
 #define DRM_IOCTL_EXYNOS_GEM_MMAP      DRM_IOWR(DRM_COMMAND_BASE + \
                DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap)
 
+#define DRM_IOCTL_EXYNOS_GEM_GET       DRM_IOWR(DRM_COMMAND_BASE + \
+               DRM_EXYNOS_GEM_GET,     struct drm_exynos_gem_info)
+
 #define DRM_IOCTL_EXYNOS_PLANE_SET_ZPOS        DRM_IOWR(DRM_COMMAND_BASE + \
                DRM_EXYNOS_PLANE_SET_ZPOS, struct drm_exynos_plane_set_zpos)
 
 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION       DRM_IOWR(DRM_COMMAND_BASE + \
                DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
 
+#define DRM_IOCTL_EXYNOS_G2D_GET_VER           DRM_IOWR(DRM_COMMAND_BASE + \
+               DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
+#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST       DRM_IOWR(DRM_COMMAND_BASE + \
+               DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
+#define DRM_IOCTL_EXYNOS_G2D_EXEC              DRM_IOWR(DRM_COMMAND_BASE + \
+               DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
+
+/* EXYNOS specific events */
+#define DRM_EXYNOS_G2D_EVENT           0x80000000
+
+struct drm_exynos_g2d_event {
+       struct drm_event        base;
+       __u64                   user_data;
+       __u32                   tv_sec;
+       __u32                   tv_usec;
+       __u32                   cmdlist_no;
+       __u32                   reserved;
+};
+
 #ifdef __KERNEL__
 
 /**
@@ -169,16 +256,14 @@ struct exynos_drm_common_hdmi_pd {
 /**
  * Platform Specific Structure for DRM based HDMI core.
  *
- * @timing: default video mode for initializing
- * @default_win: default window layer number to be used for UI.
- * @bpp: default bit per pixel.
  * @is_v13: set if hdmi version 13 is.
+ * @cfg_hpd: function pointer to configure hdmi hotplug detection pin
+ * @get_hpd: function pointer to get value of hdmi hotplug detection pin
  */
 struct exynos_drm_hdmi_pdata {
-       struct fb_videomode             timing;
-       unsigned int                    default_win;
-       unsigned int                    bpp;
-       unsigned int                    is_v13:1;
+       bool is_v13;
+       void (*cfg_hpd)(bool external);
+       int (*get_hpd)(void);
 };
 
 #endif /* __KERNEL__ */