[PATCH] md: improve raid10 "IO Barrier" concept

[~andy/linux] / include / asm-arm / atomic.h

diff --git a/include/asm-arm/atomic.h b/include/asm-arm/atomic.h
index 8ab1689ef56a1c3388fd0d25801230fd3b6516e7..f72b63309bc5c80b54fd0f9dc27a46f56a47c0e5 100644 (file)
--- a/include/asm-arm/atomic.h
+++ b/include/asm-arm/atomic.h
@@ -12,6 +12,7 @@
 #define __ASM_ARM_ATOMIC_H
 
 #include <linux/config.h>
+#include <linux/compiler.h>
 
 typedef struct { volatile int counter; } atomic_t;
 
@@ -82,11 +83,12 @@ static inline int atomic_sub_return(int i, atomic_t *v)
 
 static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
 {
-       u32 oldval, res;
+       unsigned long oldval, res;
 
        do {
                __asm__ __volatile__("@ atomic_cmpxchg\n"
                "ldrex  %1, [%2]\n"
+               "mov    %0, #0\n"
                "teq    %1, %3\n"
                "strexeq %0, %4, [%2]\n"
                    : "=&r" (res), "=&r" (oldval)
@@ -173,6 +175,17 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
 
 #endif /* __LINUX_ARM_ARCH__ */
 
+static inline int atomic_add_unless(atomic_t *v, int a, int u)
+{
+       int c, old;
+
+       c = atomic_read(v);
+       while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
+               c = old;
+       return c != u;
+}
+#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
+
 #define atomic_add(i, v)       (void) atomic_add_return(i, v)
 #define atomic_inc(v)          (void) atomic_add_return(1, v)
 #define atomic_sub(i, v)       (void) atomic_sub_return(i, v)
@@ -192,5 +205,6 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
 #define smp_mb__before_atomic_inc()    barrier()
 #define smp_mb__after_atomic_inc()     barrier()
 
+#include <asm-generic/atomic.h>
 #endif
 #endif