int port;
for (port = 0; port < uhci->rh_numports; ++port) {
- if ((inw(uhci->io_addr + USBPORTSC1 + port * 2) &
+ if ((uhci_readw(uhci, USBPORTSC1 + port * 2) &
(USBPORTSC_CCS | RWC_BITS)) ||
test_bit(port, &uhci->port_c_suspend))
return 1;
*buf = 0;
for (port = 0; port < uhci->rh_numports; ++port) {
- if ((inw(uhci->io_addr + USBPORTSC1 + port * 2) & mask) ||
+ if ((uhci_readw(uhci, USBPORTSC1 + port * 2) & mask) ||
test_bit(port, &uhci->port_c_suspend))
*buf |= (1 << (port + 1));
}
#define OK(x) len = (x); break
#define CLR_RH_PORTSTAT(x) \
- status = inw(port_addr); \
+ status = uhci_readw(uhci, port_addr); \
status &= ~(RWC_BITS|WZ_BITS); \
status &= ~(x); \
status |= RWC_BITS & (x); \
- outw(status, port_addr)
+ uhci_writew(uhci, status, port_addr)
#define SET_RH_PORTSTAT(x) \
- status = inw(port_addr); \
+ status = uhci_readw(uhci, port_addr); \
status |= (x); \
status &= ~(RWC_BITS|WZ_BITS); \
- outw(status, port_addr)
+ uhci_writew(uhci, status, port_addr)
/* UHCI controllers don't automatically stop resume signalling after 20 msec,
* so we have to poll and check timeouts in order to take care of it.
int status;
int i;
- if (inw(port_addr) & SUSPEND_BITS) {
+ if (uhci_readw(uhci, port_addr) & SUSPEND_BITS) {
CLR_RH_PORTSTAT(SUSPEND_BITS);
if (test_bit(port, &uhci->resuming_ports))
set_bit(port, &uhci->port_c_suspend);
* Experiments show that some controllers take longer, so
* we'll poll for completion. */
for (i = 0; i < 10; ++i) {
- if (!(inw(port_addr) & SUSPEND_BITS))
+ if (!(uhci_readw(uhci, port_addr) & SUSPEND_BITS))
break;
udelay(1);
}
/* Wait for the UHCI controller in HP's iLO2 server management chip.
* It can take up to 250 us to finish a reset and set the CSC bit.
*/
-static void wait_for_HP(unsigned long port_addr)
+static void wait_for_HP(struct uhci_hcd *uhci, unsigned long port_addr)
{
int i;
for (i = 10; i < 250; i += 10) {
- if (inw(port_addr) & USBPORTSC_CSC)
+ if (uhci_readw(uhci, port_addr) & USBPORTSC_CSC)
return;
udelay(10);
}
int status;
for (port = 0; port < uhci->rh_numports; ++port) {
- port_addr = uhci->io_addr + USBPORTSC1 + 2 * port;
- status = inw(port_addr);
+ port_addr = USBPORTSC1 + 2 * port;
+ status = uhci_readw(uhci, port_addr);
if (unlikely(status & USBPORTSC_PR)) {
if (time_after_eq(jiffies, uhci->ports_timeout)) {
CLR_RH_PORTSTAT(USBPORTSC_PR);
/* HP's server management chip requires
* a longer delay. */
if (uhci->wait_for_hp)
- wait_for_HP(port_addr);
+ wait_for_HP(uhci, port_addr);
/* If the port was enabled before, turning
* reset on caused a port enable change.
struct uhci_hcd *uhci = hcd_to_uhci(hcd);
int status, lstatus, retval = 0, len = 0;
unsigned int port = wIndex - 1;
- unsigned long port_addr = uhci->io_addr + USBPORTSC1 + 2 * port;
+ unsigned long port_addr = USBPORTSC1 + 2 * port;
u16 wPortChange, wPortStatus;
unsigned long flags;
goto err;
uhci_check_ports(uhci);
- status = inw(port_addr);
+ status = uhci_readw(uhci, port_addr);
/* Intel controllers report the OverCurrent bit active on.
* VIA controllers report it active off, so we'll adjust the
CLR_RH_PORTSTAT(USBPORTSC_PEC);
OK(0);
case USB_PORT_FEAT_SUSPEND:
- if (!(inw(port_addr) & USBPORTSC_SUSP)) {
+ if (!(uhci_readw(uhci, port_addr) & USBPORTSC_SUSP)) {
/* Make certain the port isn't suspended */
uhci_finish_suspend(uhci, port, port_addr);
* if the port is disabled. When this happens
* just skip the Resume signalling.
*/
- if (!(inw(port_addr) & USBPORTSC_RD))
+ if (!(uhci_readw(uhci, port_addr) &
+ USBPORTSC_RD))
uhci_finish_suspend(uhci, port,
port_addr);
else