0x18,
pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
xgifb_reg_set(P3c4, 0x19, 0x01);
- xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[0]);
- xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[1]);
+ xgifb_reg_set(P3c4, 0x16, 0x03);
+ xgifb_reg_set(P3c4, 0x16, 0x83);
mdelay(1);
xgifb_reg_set(P3c4, 0x1B, 0x03);
udelay(500);
0x18,
pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
xgifb_reg_set(P3c4, 0x19, 0x00);
- xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[2]);
- xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[3]);
+ xgifb_reg_set(P3c4, 0x16, 0x03);
+ xgifb_reg_set(P3c4, 0x16, 0x83);
xgifb_reg_set(P3c4, 0x1B, 0x00);
}
temp2 = 0;
for (i = 0; i < 4; i++) {
/* CR6B DQS fine tune delay */
- temp = pVBInfo->CR6B[pVBInfo->ram_type][i];
+ temp = XGI340_CR6B[pVBInfo->ram_type][i];
for (j = 0; j < 4; j++) {
temp1 = ((temp >> (2 * j)) & 0x03) << 2;
temp2 |= temp1;
for (i = 0x47; i <= 0x4C; i++)
xgifb_reg_set(pVBInfo->P3d4,
i,
- pVBInfo->AGPReg[i - 0x47]);
+ XGI340_AGPReg[i - 0x47]);
for (i = 0x70; i <= 0x71; i++)
xgifb_reg_set(pVBInfo->P3d4,
i,
- pVBInfo->AGPReg[6 + i - 0x70]);
+ XGI340_AGPReg[6 + i - 0x70]);
for (i = 0x74; i <= 0x77; i++)
xgifb_reg_set(pVBInfo->P3d4,
i,
- pVBInfo->AGPReg[8 + i - 0x74]);
+ XGI340_AGPReg[8 + i - 0x74]);
pci_read_config_dword(pdev, 0x50, &Temp);
Temp >>= 20;