staging: rtl8192u: fix read_nic_* functions

[~andy/linux] / drivers / staging / rtl8192u / r819xU_phy.c

diff --git a/drivers/staging/rtl8192u/r819xU_phy.c b/drivers/staging/rtl8192u/r819xU_phy.c
index a6a8f90c2748e7f157dce57e5ac7417504d2643e..60cba808c2fcf3e4baa2940d885ca761a804793e 100644 (file)
--- a/drivers/staging/rtl8192u/r819xU_phy.c
+++ b/drivers/staging/rtl8192u/r819xU_phy.c
@@ -90,7 +90,7 @@ void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask, u32
 
        if(dwBitMask!= bMaskDWord)
        {//if not "double word" write
-               OriginalValue = read_nic_dword(dev, dwRegAddr);
+               read_nic_dword(dev, dwRegAddr, &OriginalValue);
                BitShift = rtl8192_CalculateBitShift(dwBitMask);
                NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
                write_nic_dword(dev, dwRegAddr, NewValue);
@@ -111,7 +111,7 @@ u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
 {
        u32 Ret = 0, OriginalValue, BitShift;
 
-       OriginalValue = read_nic_dword(dev, dwRegAddr);
+       read_nic_dword(dev, dwRegAddr, &OriginalValue);
        BitShift = rtl8192_CalculateBitShift(dwBitMask);
        Ret =(OriginalValue & dwBitMask) >> BitShift;
 
@@ -379,6 +379,7 @@ phy_FwRFSerialRead(
        u32             retValue = 0;
        u32             Data = 0;
        u8              time = 0;
+       u32             tmp;
        //DbgPrint("FW RF CTRL\n\r");
        /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
           not execute the scheme in the initial step. Otherwise, RF-R/W will waste
@@ -394,13 +395,15 @@ phy_FwRFSerialRead(
        // 5. Trigger Fw to operate the command. bit 31
        Data |= 0x80000000;
        // 6. We can not execute read operation if bit 31 is 1.
-       while (read_nic_dword(dev, QPNR)&0x80000000)
+       read_nic_dword(dev, QPNR, &tmp);
+       while (tmp & 0x80000000)
        {
                // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
                if (time++ < 100)
                {
                        //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
                        udelay(10);
+                       read_nic_dword(dev, QPNR, &tmp);
                }
                else
                        break;
@@ -408,18 +411,20 @@ phy_FwRFSerialRead(
        // 7. Execute read operation.
        write_nic_dword(dev, QPNR, Data);
        // 8. Check if firmawre send back RF content.
-       while (read_nic_dword(dev, QPNR)&0x80000000)
+       read_nic_dword(dev, QPNR, &tmp);
+       while (tmp & 0x80000000)
        {
                // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
                if (time++ < 100)
                {
                        //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
                        udelay(10);
+                       read_nic_dword(dev, QPNR, &tmp);
                }
                else
                        return  (0);
        }
-       retValue = read_nic_dword(dev, RF_DATA);
+       read_nic_dword(dev, RF_DATA, &retValue);
 
        return  (retValue);
 
@@ -440,6 +445,7 @@ phy_FwRFSerialWrite(
                u32                             Data    )
 {
        u8      time = 0;
+       u32     tmp;
 
        //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
        /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
@@ -458,13 +464,15 @@ phy_FwRFSerialWrite(
        Data |= 0x80000000;
 
        // 6. Write operation. We can not write if bit 31 is 1.
-       while (read_nic_dword(dev, QPNR)&0x80000000)
+       read_nic_dword(dev, QPNR, &tmp);
+       while (tmp & 0x80000000)
        {
                // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
                if (time++ < 100)
                {
                        //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
                        udelay(10);
+                       read_nic_dword(dev, QPNR, &tmp);
                }
                else
                        break;
@@ -710,7 +718,7 @@ u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock, RF9
                //
                // Write Data to register and readback
                //
-               switch(CheckBlock)
+               switch (CheckBlock)
                {
                case HW90_BLOCK_MAC:
                        RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!");
@@ -719,7 +727,7 @@ u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock, RF9
                case HW90_BLOCK_PHY0:
                case HW90_BLOCK_PHY1:
                        write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
-                       dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
+                       read_nic_dword(dev, WriteAddr[CheckBlock], &dwRegRead);
                        break;
 
                case HW90_BLOCK_RF:
@@ -770,11 +778,11 @@ void rtl8192_BB_Config_ParaFile(struct net_device *dev)
        **************************************/
 
        /*--set BB Global Reset--*/
-       bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
+       read_nic_byte(dev, BB_GLOBAL_RESET, &bRegValue);
        write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
        mdelay(50);
        /*---set BB reset Active---*/
-       dwRegValue = read_nic_dword(dev, CPU_GEN);
+       read_nic_dword(dev, CPU_GEN, &dwRegValue);
        write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
 
        /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
@@ -795,7 +803,7 @@ void rtl8192_BB_Config_ParaFile(struct net_device *dev)
        rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
 
        /*----Set BB reset de-Active----*/
-       dwRegValue = read_nic_dword(dev, CPU_GEN);
+       read_nic_dword(dev, CPU_GEN, &dwRegValue);
        write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
 
        /*----BB AGC table Initialization----*/
@@ -846,36 +854,32 @@ void rtl8192_BBConfig(struct net_device *dev)
 void rtl8192_phy_getTxPower(struct net_device *dev)
 {
        struct r8192_priv *priv = ieee80211_priv(dev);
-       priv->MCSTxPowerLevelOriginalOffset[0] =
-               read_nic_dword(dev, rTxAGC_Rate18_06);
-       priv->MCSTxPowerLevelOriginalOffset[1] =
-               read_nic_dword(dev, rTxAGC_Rate54_24);
-       priv->MCSTxPowerLevelOriginalOffset[2] =
-               read_nic_dword(dev, rTxAGC_Mcs03_Mcs00);
-       priv->MCSTxPowerLevelOriginalOffset[3] =
-               read_nic_dword(dev, rTxAGC_Mcs07_Mcs04);
-       priv->MCSTxPowerLevelOriginalOffset[4] =
-               read_nic_dword(dev, rTxAGC_Mcs11_Mcs08);
-       priv->MCSTxPowerLevelOriginalOffset[5] =
-               read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
+       u8 tmp;
+       read_nic_dword(dev, rTxAGC_Rate18_06, &priv->MCSTxPowerLevelOriginalOffset[0]);
+       read_nic_dword(dev, rTxAGC_Rate54_24, &priv->MCSTxPowerLevelOriginalOffset[1]);
+       read_nic_dword(dev, rTxAGC_Mcs03_Mcs00, &priv->MCSTxPowerLevelOriginalOffset[2]);
+       read_nic_dword(dev, rTxAGC_Mcs07_Mcs04, &priv->MCSTxPowerLevelOriginalOffset[3]);
+       read_nic_dword(dev, rTxAGC_Mcs11_Mcs08, &priv->MCSTxPowerLevelOriginalOffset[4]);
+       read_nic_dword(dev, rTxAGC_Mcs15_Mcs12, &priv->MCSTxPowerLevelOriginalOffset[5]);
 
        // read rx initial gain
-       priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
-       priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
-       priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
-       priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
+       read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
+       read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
+       read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
+       read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
        RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
                priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
                priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
 
        // read framesync
-       priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
-       priv->framesyncC34 = read_nic_byte(dev, rOFDM0_RxDetector2);
+       read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
+       read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
+       priv->framesyncC34 = tmp;
        RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
                rOFDM0_RxDetector3, priv->framesync);
 
        // read SIFS (save the value read fome MACPHY_REG.txt)
-       priv->SifsTime = read_nic_word(dev, SIFS);
+       read_nic_word(dev, SIFS, &priv->SifsTime);
 
        return;
 }
@@ -892,7 +896,7 @@ void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
        u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
        u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
 
-       switch(priv->rf_chip)
+       switch (priv->rf_chip)
        {
        case RF_8256:
                PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement
@@ -917,7 +921,7 @@ void rtl8192_phy_RFConfig(struct net_device *dev)
 {
        struct r8192_priv *priv = ieee80211_priv(dev);
 
-       switch(priv->rf_chip)
+       switch (priv->rf_chip)
        {
                case RF_8256:
                        PHY_RF8256_Config(dev);
@@ -956,7 +960,7 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, RF90_RADIO_PATH_E
        //u32* pRFArray;
        u8 ret = 0;
 
-       switch(eRFPath){
+       switch (eRFPath){
        case RF90_PATH_A:
                for(i = 0;i<RadioA_ArrayLength; i=i+2){
 
@@ -1026,7 +1030,7 @@ void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
        u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
        u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
 
-       switch(priv->rf_chip)
+       switch (priv->rf_chip)
        {
        case RF_8225:
 #ifdef TO_DO_LIST
@@ -1071,10 +1075,10 @@ bool rtl8192_SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerS
 
        priv->SetRFPowerStateInProgress = true;
 
-       switch(priv->rf_chip)
+       switch (priv->rf_chip)
        {
                case RF_8256:
-               switch( eRFPowerState )
+               switch ( eRFPowerState )
                {
                        case eRfOn:
        //RF-A, RF-B
@@ -1129,10 +1133,10 @@ bool rtl8192_SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerS
        {
                // Update current RF state variable.
                pHalData->eRFPowerState = eRFPowerState;
-               switch(pHalData->RFChipID )
+               switch (pHalData->RFChipID )
                {
                        case RF_8256:
-               switch(pHalData->eRFPowerState)
+               switch (pHalData->eRFPowerState)
                                {
                                case eRfOff:
                                        //
@@ -1283,7 +1287,7 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage, u
 
                // <3> Fill up RF dependent command.
                RfDependCmdCnt = 0;
-               switch( priv->rf_chip )
+               switch ( priv->rf_chip )
                {
                case RF_8225:
                        if (!(channel >= 1 && channel <= 14))
@@ -1321,7 +1325,7 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage, u
 
 
                do{
-                       switch(*stage)
+                       switch (*stage)
                        {
                        case 0:
                                CurrentCmd=&PreCommonCmd[*step];
@@ -1349,7 +1353,7 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage, u
                                }
                        }
 
-                       switch(CurrentCmd->CmdID)
+                       switch (CurrentCmd->CmdID)
                        {
                        case CmdID_SetTxPowerLevel:
                                if(priv->card_8192_version == (u8)VERSION_819xU_A) //xiong: consider it later!
@@ -1452,7 +1456,7 @@ if (0) //to test current channel from RF reg 0x7.
        }
 }
        //--------------------------------------------
-       switch(priv->ieee80211->mode)
+       switch (priv->ieee80211->mode)
        {
        case WIRELESS_MODE_A:
        case WIRELESS_MODE_N_5G:
@@ -1525,9 +1529,9 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
        }
 
        //<1>Set MAC register
-       regBwOpMode = read_nic_byte(dev, BW_OPMODE);
+       read_nic_byte(dev, BW_OPMODE, &regBwOpMode);
 
-       switch(priv->CurrentChannelBW)
+       switch (priv->CurrentChannelBW)
        {
                case HT_CHANNEL_WIDTH_20:
                        regBwOpMode |= BW_OPMODE_20MHZ;
@@ -1547,7 +1551,7 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
        }
 
        //<2>Set PHY related register
-       switch(priv->CurrentChannelBW)
+       switch (priv->CurrentChannelBW)
        {
                case HT_CHANNEL_WIDTH_20:
                        // Add by Vivi 20071119
@@ -1617,7 +1621,7 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
        //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
 
        //<3>Set RF related register
-       switch( priv->rf_chip )
+       switch ( priv->rf_chip )
        {
                case RF_8225:
 #ifdef TO_DO_LIST
@@ -1704,7 +1708,7 @@ extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
 
        Operation = priv->InitialGainOperateType;
 
-       switch(Operation)
+       switch (Operation)
        {
                case IG_Backup:
                        RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");