]> Pileus Git - ~andy/linux/blobdiff - drivers/scsi/be2iscsi/be_main.h
[SCSI] be2iscsi: Fix WRB_Q posting to support Dual Chute mode
[~andy/linux] / drivers / scsi / be2iscsi / be_main.h
index d0bbf373cb2e54b327ff5b12889c8e72656e5053..410efc72bfd9c78f70a71912c1aaf0eb6d68372f 100644 (file)
@@ -34,7 +34,6 @@
 #include <scsi/libiscsi.h>
 #include <scsi/scsi_transport_iscsi.h>
 
-#include "be.h"
 #define DRV_NAME               "be2iscsi"
 #define BUILD_STR              "10.0.467.0"
 #define BE_NAME                        "Emulex OneConnect" \
 
 #define BEISCSI_MSI_NAME 20 /* size of msi_name string */
 
-#define MEM_DESCR_OFFSET 7
+#define MEM_DESCR_OFFSET 8
 #define BEISCSI_DEFQ_HDR 1
 #define BEISCSI_DEFQ_DATA 0
 enum be_mem_enum {
@@ -170,20 +169,21 @@ enum be_mem_enum {
        HWI_MEM_WRBH,
        HWI_MEM_SGLH,
        HWI_MEM_SGE,
-       HWI_MEM_TEMPLATE_HDR,
-       HWI_MEM_ASYNC_HEADER_BUF_ULP0,
+       HWI_MEM_TEMPLATE_HDR_ULP0,
+       HWI_MEM_ASYNC_HEADER_BUF_ULP0,  /* 6 */
        HWI_MEM_ASYNC_DATA_BUF_ULP0,
        HWI_MEM_ASYNC_HEADER_RING_ULP0,
        HWI_MEM_ASYNC_DATA_RING_ULP0,
        HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
-       HWI_MEM_ASYNC_DATA_HANDLE_ULP0,
+       HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */
        HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
-       HWI_MEM_ASYNC_HEADER_BUF_ULP1,
+       HWI_MEM_TEMPLATE_HDR_ULP1,
+       HWI_MEM_ASYNC_HEADER_BUF_ULP1,  /* 14 */
        HWI_MEM_ASYNC_DATA_BUF_ULP1,
        HWI_MEM_ASYNC_HEADER_RING_ULP1,
        HWI_MEM_ASYNC_DATA_RING_ULP1,
        HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
-       HWI_MEM_ASYNC_DATA_HANDLE_ULP1,
+       HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */
        HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
        ISCSI_MEM_GLOBAL_HEADER,
        SE_MEM_MAX
@@ -279,6 +279,25 @@ struct invalidate_command_table {
        unsigned short cid;
 } __packed;
 
+#define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
+       (phwi_ctrlr->wrb_context[cri].ulp_num)
+struct hwi_wrb_context {
+       struct list_head wrb_handle_list;
+       struct list_head wrb_handle_drvr_list;
+       struct wrb_handle **pwrb_handle_base;
+       struct wrb_handle **pwrb_handle_basestd;
+       struct iscsi_wrb *plast_wrb;
+       unsigned short alloc_index;
+       unsigned short free_index;
+       unsigned short wrb_handles_available;
+       unsigned short cid;
+       uint8_t ulp_num;        /* ULP to which CID binded */
+       uint16_t register_set;
+       uint16_t doorbell_format;
+       uint32_t doorbell_offset;
+};
+
+#include "be.h"
 #define chip_be2(phba)      (phba->generation == BE_GEN2)
 #define chip_be3_r(phba)    (phba->generation == BE_GEN3)
 #define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
@@ -954,21 +973,6 @@ struct be_ring {
                                 */
 };
 
-#define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
-       (phwi_ctrlr->wrb_context[cri].ulp_num)
-struct hwi_wrb_context {
-       struct list_head wrb_handle_list;
-       struct list_head wrb_handle_drvr_list;
-       struct wrb_handle **pwrb_handle_base;
-       struct wrb_handle **pwrb_handle_basestd;
-       struct iscsi_wrb *plast_wrb;
-       unsigned short alloc_index;
-       unsigned short free_index;
-       unsigned short wrb_handles_available;
-       unsigned short cid;
-       uint8_t ulp_num;        /* ULP to which CID binded */
-};
-
 struct hwi_controller {
        struct list_head io_sgl_list;
        struct list_head eh_sgl_list;