Merge branch 'hpfs' from Mikulas Patocka

[~andy/linux] / drivers / pci / quirks.c

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 7d68aeebf56b1a53d447bd0e152643d85d06ea44..e85d23044ae0dcd43b20d0b840a71e551286a310 100644 (file)
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -1022,6 +1022,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk
 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
 
 /*
  *     Serverworks CSB5 IDE does not fully support native mode
@@ -1832,7 +1834,6 @@ static void quirk_e100_interrupt(struct pci_dev *dev)
        u16 command, pmcsr;
        u8 __iomem *csr;
        u8 cmd_hi;
-       int pm;
 
        switch (dev->device) {
        /* PCI IDs taken from drivers/net/e100.c */
@@ -1870,9 +1871,8 @@ static void quirk_e100_interrupt(struct pci_dev *dev)
         * Check that the device is in the D0 power state. If it's not,
         * there is no point to look any further.
         */
-       pm = pci_find_capability(dev, PCI_CAP_ID_PM);
-       if (pm) {
-               pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
+       if (dev->pm_cap) {
+               pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
                if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
                        return;
        }
@@ -2865,6 +2865,31 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
 
 
+/*
+ * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.  To
+ * work around this, query the size it should be configured to by the device and
+ * modify the resource end to correspond to this new size.
+ */
+static void quirk_intel_ntb(struct pci_dev *dev)
+{
+       int rc;
+       u8 val;
+
+       rc = pci_read_config_byte(dev, 0x00D0, &val);
+       if (rc)
+               return;
+
+       dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
+
+       rc = pci_read_config_byte(dev, 0x00D1, &val);
+       if (rc)
+               return;
+
+       dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
+
 static ktime_t fixup_debug_start(struct pci_dev *dev,
                                 void (*fn)(struct pci_dev *dev))
 {