b43: HT-PHY: implement RSSI polling

[~andy/linux] / drivers / net / wireless / b43 / phy_ht.h

diff --git a/drivers/net/wireless/b43/phy_ht.h b/drivers/net/wireless/b43/phy_ht.h
index 6544c4293b34ddc0f3980041d7f29ce547fb5212..165c5014b7c8eb0b80e7d388f4b00fa63d8d6406 100644 (file)
--- a/drivers/net/wireless/b43/phy_ht.h
+++ b/drivers/net/wireless/b43/phy_ht.h
@@ -12,18 +12,41 @@
 #define B43_PHY_HT_TABLE_ADDR                  0x072 /* Table address */
 #define B43_PHY_HT_TABLE_DATALO                        0x073 /* Table data low */
 #define B43_PHY_HT_TABLE_DATAHI                        0x074 /* Table data high */
+#define B43_PHY_HT_CLASS_CTL                   0x0B0 /* Classifier control */
+#define  B43_PHY_HT_CLASS_CTL_CCK_EN           0x0001 /* CCK enable */
+#define  B43_PHY_HT_CLASS_CTL_OFDM_EN          0x0002 /* OFDM enable */
+#define  B43_PHY_HT_CLASS_CTL_WAITED_EN                0x0004 /* Waited enable */
+#define B43_PHY_HT_IQLOCAL_CMDGCTL             0x0C2   /* I/Q LO cal command G control */
+#define B43_PHY_HT_SAMP_CMD                    0x0C3   /* Sample command */
+#define  B43_PHY_HT_SAMP_CMD_STOP              0x0002  /* Stop */
+#define B43_PHY_HT_SAMP_LOOP_CNT               0x0C4   /* Sample loop count */
+#define B43_PHY_HT_SAMP_WAIT_CNT               0x0C5   /* Sample wait count */
+#define B43_PHY_HT_SAMP_DEP_CNT                        0x0C6   /* Sample depth count */
+#define B43_PHY_HT_SAMP_STAT                   0x0C7   /* Sample status */
 #define B43_PHY_HT_BW1                         0x1CE
 #define B43_PHY_HT_BW2                         0x1CF
 #define B43_PHY_HT_BW3                         0x1D0
 #define B43_PHY_HT_BW4                         0x1D1
 #define B43_PHY_HT_BW5                         0x1D2
 #define B43_PHY_HT_BW6                         0x1D3
+#define B43_PHY_HT_TXPCTL_CMD_C1               0x1E7   /* TX power control command */
+#define  B43_PHY_HT_TXPCTL_CMD_C1_INIT         0x007F  /* Init */
+#define  B43_PHY_HT_TXPCTL_CMD_C1_COEFF                0x2000  /* Power control coefficients */
+#define  B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN     0x4000  /* Hardware TX power control enable */
+#define  B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN       0x8000  /* TX power control enable */
+#define B43_PHY_HT_TXPCTL_CMD_C2               0x222
+#define  B43_PHY_HT_TXPCTL_CMD_C2_INIT         0x007F
+#define B43_PHY_HT_RSSI_C1                     0x219
+#define B43_PHY_HT_RSSI_C2                     0x21A
+#define B43_PHY_HT_RSSI_C3                     0x21B
 
 #define B43_PHY_HT_C1_CLIP1THRES               B43_PHY_OFDM(0x00E)
 #define B43_PHY_HT_C2_CLIP1THRES               B43_PHY_OFDM(0x04E)
 #define B43_PHY_HT_C3_CLIP1THRES               B43_PHY_OFDM(0x08E)
 
 #define B43_PHY_HT_RF_SEQ_MODE                 B43_PHY_EXTG(0x000)
+#define  B43_PHY_HT_RF_SEQ_MODE_CA_OVER                0x0001  /* Core active override */
+#define  B43_PHY_HT_RF_SEQ_MODE_TR_OVER                0x0002  /* Trigger override */
 #define B43_PHY_HT_RF_SEQ_TRIG                 B43_PHY_EXTG(0x003)
 #define  B43_PHY_HT_RF_SEQ_TRIG_RX2TX          0x0001 /* RX2TX */
 #define  B43_PHY_HT_RF_SEQ_TRIG_TX2RX          0x0002 /* TX2RX */
@@ -36,12 +59,21 @@
 
 #define B43_PHY_HT_RF_CTL1                     B43_PHY_EXTG(0x010)
 
-#define B43_PHY_HT_AFE_CTL1                    B43_PHY_EXTG(0x110)
-#define B43_PHY_HT_AFE_CTL2                    B43_PHY_EXTG(0x111)
-#define B43_PHY_HT_AFE_CTL3                    B43_PHY_EXTG(0x114)
-#define B43_PHY_HT_AFE_CTL4                    B43_PHY_EXTG(0x115)
-#define B43_PHY_HT_AFE_CTL5                    B43_PHY_EXTG(0x118)
-#define B43_PHY_HT_AFE_CTL6                    B43_PHY_EXTG(0x119)
+#define B43_PHY_HT_RF_CTL_INT_C1               B43_PHY_EXTG(0x04c)
+#define B43_PHY_HT_RF_CTL_INT_C2               B43_PHY_EXTG(0x06c)
+#define B43_PHY_HT_RF_CTL_INT_C3               B43_PHY_EXTG(0x08c)
+
+#define B43_PHY_HT_AFE_C1_OVER                 B43_PHY_EXTG(0x110)
+#define B43_PHY_HT_AFE_C1                      B43_PHY_EXTG(0x111)
+#define B43_PHY_HT_AFE_C2_OVER                 B43_PHY_EXTG(0x114)
+#define B43_PHY_HT_AFE_C2                      B43_PHY_EXTG(0x115)
+#define B43_PHY_HT_AFE_C3_OVER                 B43_PHY_EXTG(0x118)
+#define B43_PHY_HT_AFE_C3                      B43_PHY_EXTG(0x119)
+
+#define B43_PHY_HT_TXPCTL_CMD_C3               B43_PHY_EXTG(0x164)
+#define  B43_PHY_HT_TXPCTL_CMD_C3_INIT         0x007F
+
+#define B43_PHY_HT_TEST                                B43_PHY_N_BMODE(0x00A)
 
 
 /* Values for PHY registers used on channel switching */
@@ -56,6 +88,14 @@ struct b43_phy_ht_channeltab_e_phy {
 
 
 struct b43_phy_ht {
+       u16 rf_ctl_int_save[3];
+
+       bool tx_pwr_ctl;
+       u8 tx_pwr_idx[3];
+
+       s32 bb_mult_save[3];
+
+       u8 idle_tssi[3];
 };