phy->reset_delay_us = 100;
phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
- phy->ops.read_phy_reg = e1000_read_phy_reg_hv;
- phy->ops.read_phy_reg_locked = e1000_read_phy_reg_hv_locked;
+ phy->ops.read_reg = e1000_read_phy_reg_hv;
+ phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
- phy->ops.write_phy_reg = e1000_write_phy_reg_hv;
- phy->ops.write_phy_reg_locked = e1000_write_phy_reg_hv_locked;
+ phy->ops.write_reg = e1000_write_phy_reg_hv;
+ phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
phy->id = e1000_phy_unknown;
phy->ops.force_speed_duplex =
e1000_phy_force_speed_duplex_82577;
phy->ops.get_cable_length = e1000_get_cable_length_82577;
- phy->ops.get_phy_info = e1000_get_phy_info_82577;
- phy->ops.commit_phy = e1000e_phy_sw_reset;
+ phy->ops.get_info = e1000_get_phy_info_82577;
+ phy->ops.commit = e1000e_phy_sw_reset;
}
return ret_val;
*/
ret_val = e1000e_determine_phy_address(hw);
if (ret_val) {
- hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
- hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
+ phy->ops.write_reg = e1000e_write_phy_reg_bm;
+ phy->ops.read_reg = e1000e_read_phy_reg_bm;
ret_val = e1000e_determine_phy_address(hw);
if (ret_val)
return ret_val;
case IGP03E1000_E_PHY_ID:
phy->type = e1000_phy_igp_3;
phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
- phy->ops.read_phy_reg_locked = e1000e_read_phy_reg_igp_locked;
- phy->ops.write_phy_reg_locked = e1000e_write_phy_reg_igp_locked;
+ phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
+ phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
break;
case IFE_E_PHY_ID:
case IFE_PLUS_E_PHY_ID:
case BME1000_E_PHY_ID:
phy->type = e1000_phy_bm;
phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
- hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
- hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
- hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
+ phy->ops.read_reg = e1000e_read_phy_reg_bm;
+ phy->ops.write_reg = e1000e_write_phy_reg_bm;
+ phy->ops.commit = e1000e_phy_sw_reset;
break;
default:
return -E1000_ERR_PHY;
s32 ret_val;
u16 word_addr, reg_data, reg_addr, phy_page = 0;
- ret_val = hw->phy.ops.acquire_phy(hw);
+ ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
return ret_val;
reg_addr &= PHY_REG_MASK;
reg_addr |= phy_page;
- ret_val = phy->ops.write_phy_reg_locked(hw,
+ ret_val = phy->ops.write_reg_locked(hw,
(u32)reg_addr,
reg_data);
if (ret_val)
}
out:
- hw->phy.ops.release_phy(hw);
+ hw->phy.ops.release(hw);
return ret_val;
}
goto out;
/* Wrap the whole flow with the sw flag */
- ret_val = hw->phy.ops.acquire_phy(hw);
+ ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
goto out;
/* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
if (link) {
if (hw->phy.type == e1000_phy_82578) {
- ret_val = hw->phy.ops.read_phy_reg_locked(hw,
- BM_CS_STATUS,
+ ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
&status_reg);
if (ret_val)
goto release;
}
if (hw->phy.type == e1000_phy_82577) {
- ret_val = hw->phy.ops.read_phy_reg_locked(hw,
- HV_M_STATUS,
+ ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
&status_reg);
if (ret_val)
goto release;
}
/* Link stall fix for link up */
- ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19),
+ ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
0x0100);
if (ret_val)
goto release;
} else {
/* Link stall fix for link down */
- ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19),
+ ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
0x4100);
if (ret_val)
goto release;
ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
release:
- hw->phy.ops.release_phy(hw);
+ hw->phy.ops.release(hw);
out:
return ret_val;
}
if (hw->mac.type != e1000_pchlan)
return ret_val;
- ret_val = hw->phy.ops.acquire_phy(hw);
+ ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
return ret_val;
mac_reg = er32(PHY_CTRL);
- ret_val = hw->phy.ops.read_phy_reg_locked(hw, HV_OEM_BITS, &oem_reg);
+ ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
if (ret_val)
goto out;
}
/* Restart auto-neg to activate the bits */
oem_reg |= HV_OEM_BITS_RESTART_AN;
- ret_val = hw->phy.ops.write_phy_reg_locked(hw, HV_OEM_BITS, oem_reg);
+ ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
out:
- hw->phy.ops.release_phy(hw);
+ hw->phy.ops.release(hw);
return ret_val;
}
}
/* Select page 0 */
- ret_val = hw->phy.ops.acquire_phy(hw);
+ ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
return ret_val;
ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
if (ret_val)
goto out;
- hw->phy.ops.release_phy(hw);
+ hw->phy.ops.release(hw);
/*
* Configure the K1 Si workaround during phy reset assuming there is
goto out;
}
- nvm->ops.acquire_nvm(hw);
+ nvm->ops.acquire(hw);
ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
if (ret_val) {
}
}
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
out:
if (ret_val)
return -E1000_ERR_NVM;
}
- nvm->ops.acquire_nvm(hw);
+ nvm->ops.acquire(hw);
for (i = 0; i < words; i++) {
dev_spec->shadow_ram[offset+i].modified = 1;
dev_spec->shadow_ram[offset+i].value = data[i];
}
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
return 0;
}
if (nvm->type != e1000_nvm_flash_sw)
goto out;
- nvm->ops.acquire_nvm(hw);
+ nvm->ops.acquire(hw);
/*
* We're writing to the opposite bank so if we're on bank 1,
old_bank_offset = 0;
ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
if (ret_val) {
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
goto out;
}
} else {
new_bank_offset = 0;
ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
if (ret_val) {
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
goto out;
}
}
if (ret_val) {
/* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
e_dbg("Flash commit failed.\n");
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
goto out;
}
act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
if (ret_val) {
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
goto out;
}
data &= 0xBFFF;
act_offset * 2 + 1,
(u8)(data >> 8));
if (ret_val) {
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
goto out;
}
act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
if (ret_val) {
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
goto out;
}
dev_spec->shadow_ram[i].value = 0xFFFF;
}
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
/*
* Reload the EEPROM, or else modifications will not appear
union ich8_hws_flash_status hsfsts;
u32 gfpreg;
- nvm->ops.acquire_nvm(hw);
+ nvm->ops.acquire(hw);
gfpreg = er32flash(ICH_FLASH_GFPREG);
hsfsts.hsf_status.flockdn = true;
ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
- nvm->ops.release_nvm(hw);
+ nvm->ops.release(hw);
}
/**
* Reset the phy after disabling host wakeup to reset the Rx buffer.
*/
if (hw->phy.type == e1000_phy_82578) {
- hw->phy.ops.read_phy_reg(hw, BM_WUC, &i);
+ hw->phy.ops.read_reg(hw, BM_WUC, &i);
ret_val = e1000_phy_hw_reset_ich8lan(hw);
if (ret_val)
return ret_val;
ew32(FCTTV, hw->fc.pause_time);
if ((hw->phy.type == e1000_phy_82578) ||
(hw->phy.type == e1000_phy_82577)) {
- ret_val = hw->phy.ops.write_phy_reg(hw,
+ ret_val = hw->phy.ops.write_reg(hw,
PHY_REG(BM_PORT_CTRL_PAGE, 27),
hw->fc.pause_time);
if (ret_val)
return ret_val;
break;
case e1000_phy_ife:
- ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
+ ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
®_data);
if (ret_val)
return ret_val;
reg_data |= IFE_PMC_AUTO_MDIX;
break;
}
- ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
+ ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
reg_data);
if (ret_val)
return ret_val;
**/
static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
{
- return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
+ return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
(u16)hw->mac.ledctl_mode1);
}
**/
static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
{
- return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
+ return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
(u16)hw->mac.ledctl_default);
}
}
}
- return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
+ return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
}
/**
}
}
- return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
+ return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
}
/**
/* Clear PHY statistics registers */
if ((hw->phy.type == e1000_phy_82578) ||
(hw->phy.type == e1000_phy_82577)) {
- hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data);
- hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
+ hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
}
}
};
static struct e1000_phy_operations ich8_phy_ops = {
- .acquire_phy = e1000_acquire_swflag_ich8lan,
+ .acquire = e1000_acquire_swflag_ich8lan,
.check_reset_block = e1000_check_reset_block_ich8lan,
- .commit_phy = NULL,
+ .commit = NULL,
.force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan,
.get_cfg_done = e1000_get_cfg_done_ich8lan,
.get_cable_length = e1000e_get_cable_length_igp_2,
- .get_phy_info = e1000_get_phy_info_ich8lan,
- .read_phy_reg = e1000e_read_phy_reg_igp,
- .release_phy = e1000_release_swflag_ich8lan,
- .reset_phy = e1000_phy_hw_reset_ich8lan,
+ .get_info = e1000_get_phy_info_ich8lan,
+ .read_reg = e1000e_read_phy_reg_igp,
+ .release = e1000_release_swflag_ich8lan,
+ .reset = e1000_phy_hw_reset_ich8lan,
.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
- .write_phy_reg = e1000e_write_phy_reg_igp,
+ .write_reg = e1000e_write_phy_reg_igp,
};
static struct e1000_nvm_operations ich8_nvm_ops = {
- .acquire_nvm = e1000_acquire_nvm_ich8lan,
- .read_nvm = e1000_read_nvm_ich8lan,
- .release_nvm = e1000_release_nvm_ich8lan,
- .update_nvm = e1000_update_nvm_checksum_ich8lan,
+ .acquire = e1000_acquire_nvm_ich8lan,
+ .read = e1000_read_nvm_ich8lan,
+ .release = e1000_release_nvm_ich8lan,
+ .update = e1000_update_nvm_checksum_ich8lan,
.valid_led_default = e1000_valid_led_default_ich8lan,
- .validate_nvm = e1000_validate_nvm_checksum_ich8lan,
- .write_nvm = e1000_write_nvm_ich8lan,
+ .validate = e1000_validate_nvm_checksum_ich8lan,
+ .write = e1000_write_nvm_ich8lan,
};
struct e1000_info e1000_ich8_info = {
projects / ~andy / linux / blobdiff