[BNX2]: Update version and rel date.

[~andy/linux] / drivers / net / bnx2.c

diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 52fe620e1a4c11e8d528310ae72deefdd9955087..fc2f1d1c7ead437f4665539b9b7e61c461ac527f 100644 (file)
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -53,11 +53,12 @@
 
 #include "bnx2.h"
 #include "bnx2_fw.h"
+#include "bnx2_fw2.h"
 
 #define DRV_MODULE_NAME                "bnx2"
 #define PFX DRV_MODULE_NAME    ": "
-#define DRV_MODULE_VERSION     "1.4.45"
-#define DRV_MODULE_RELDATE     "September 29, 2006"
+#define DRV_MODULE_VERSION     "1.5.1"
+#define DRV_MODULE_RELDATE     "November 15, 2006"
 
 #define RUN_AT(x) (jiffies + (x))
 
@@ -85,6 +86,7 @@ typedef enum {
        NC370F,
        BCM5708,
        BCM5708S,
+       BCM5709,
 } board_t;
 
 /* indexed by board_t, above */
@@ -98,6 +100,7 @@ static const struct {
        { "HP NC370F Multifunction Gigabit Server Adapter" },
        { "Broadcom NetXtreme II BCM5708 1000Base-T" },
        { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
+       { "Broadcom NetXtreme II BCM5709 1000Base-T" },
        };
 
 static struct pci_device_id bnx2_pci_tbl[] = {
@@ -115,6 +118,8 @@ static struct pci_device_id bnx2_pci_tbl[] = {
          PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
        { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
          PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
+       { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
+         PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
        { 0, }
 };
 
@@ -2410,7 +2415,10 @@ bnx2_init_cpus(struct bnx2 *bp)
        cpu_reg.spad_base = BNX2_RXP_SCRATCH;
        cpu_reg.mips_view_base = 0x8000000;
 
-       fw = &bnx2_rxp_fw_06;
+       if (CHIP_NUM(bp) == CHIP_NUM_5709)
+               fw = &bnx2_rxp_fw_09;
+       else
+               fw = &bnx2_rxp_fw_06;
 
        rc = load_cpu_fw(bp, &cpu_reg, fw);
        if (rc)
@@ -2430,7 +2438,10 @@ bnx2_init_cpus(struct bnx2 *bp)
        cpu_reg.spad_base = BNX2_TXP_SCRATCH;
        cpu_reg.mips_view_base = 0x8000000;
 
-       fw = &bnx2_txp_fw_06;
+       if (CHIP_NUM(bp) == CHIP_NUM_5709)
+               fw = &bnx2_txp_fw_09;
+       else
+               fw = &bnx2_txp_fw_06;
 
        rc = load_cpu_fw(bp, &cpu_reg, fw);
        if (rc)
@@ -2450,7 +2461,10 @@ bnx2_init_cpus(struct bnx2 *bp)
        cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
        cpu_reg.mips_view_base = 0x8000000;
 
-       fw = &bnx2_tpat_fw_06;
+       if (CHIP_NUM(bp) == CHIP_NUM_5709)
+               fw = &bnx2_tpat_fw_09;
+       else
+               fw = &bnx2_tpat_fw_06;
 
        rc = load_cpu_fw(bp, &cpu_reg, fw);
        if (rc)
@@ -2470,12 +2484,36 @@ bnx2_init_cpus(struct bnx2 *bp)
        cpu_reg.spad_base = BNX2_COM_SCRATCH;
        cpu_reg.mips_view_base = 0x8000000;
 
-       fw = &bnx2_com_fw_06;
+       if (CHIP_NUM(bp) == CHIP_NUM_5709)
+               fw = &bnx2_com_fw_09;
+       else
+               fw = &bnx2_com_fw_06;
 
        rc = load_cpu_fw(bp, &cpu_reg, fw);
        if (rc)
                goto init_cpu_err;
 
+       /* Initialize the Command Processor. */
+       cpu_reg.mode = BNX2_CP_CPU_MODE;
+       cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
+       cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
+       cpu_reg.state = BNX2_CP_CPU_STATE;
+       cpu_reg.state_value_clear = 0xffffff;
+       cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
+       cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
+       cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
+       cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
+       cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
+       cpu_reg.spad_base = BNX2_CP_SCRATCH;
+       cpu_reg.mips_view_base = 0x8000000;
+
+       if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+               fw = &bnx2_cp_fw_09;
+
+               load_cpu_fw(bp, &cpu_reg, fw);
+               if (rc)
+                       goto init_cpu_err;
+       }
 init_cpu_err:
        bnx2_gunzip_end(bp);
        return rc;
@@ -5820,10 +5858,15 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
        bp->phy_addr = 1;
 
        /* Disable WOL support if we are running on a SERDES chip. */
-       if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
+       if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+               if (CHIP_BOND_ID(bp) != BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
+                       bp->phy_flags |= PHY_SERDES_FLAG;
+       } else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
                bp->phy_flags |= PHY_SERDES_FLAG;
+
+       if (bp->phy_flags & PHY_SERDES_FLAG) {
                bp->flags |= NO_WOL_FLAG;
-               if (CHIP_NUM(bp) == CHIP_NUM_5708) {
+               if (CHIP_NUM(bp) != CHIP_NUM_5706) {
                        bp->phy_addr = 2;
                        reg = REG_RD_IND(bp, bp->shmem_base +
                                         BNX2_SHARED_HW_CFG_CONFIG);