Merge branches 'dma-debug', 'iommu/fixes', 'arm/tegra', 'arm/exynos', 'x86/amd',...

[~andy/linux] / drivers / iommu / amd_iommu_types.h

diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h
index d0dab865a8b8bc8c6f0cd6603f6b4c9e2110e200..c9aa3d079ff0377c376012bb5130b62e6bcefb8e 100644 (file)
--- a/drivers/iommu/amd_iommu_types.h
+++ b/drivers/iommu/amd_iommu_types.h
@@ -152,6 +152,7 @@
 #define CMD_INV_DEV_ENTRY       0x02
 #define CMD_INV_IOMMU_PAGES    0x03
 #define CMD_INV_IOTLB_PAGES    0x04
+#define CMD_INV_IRT            0x05
 #define CMD_COMPLETE_PPR       0x07
 #define CMD_INV_ALL            0x08
 
@@ -175,6 +176,7 @@
 #define DEV_ENTRY_EX            0x67
 #define DEV_ENTRY_SYSMGT1       0x68
 #define DEV_ENTRY_SYSMGT2       0x69
+#define DEV_ENTRY_IRQ_TBL_EN   0x80
 #define DEV_ENTRY_INIT_PASS     0xb8
 #define DEV_ENTRY_EINT_PASS     0xb9
 #define DEV_ENTRY_NMI_PASS      0xba
@@ -183,6 +185,8 @@
 #define DEV_ENTRY_MODE_MASK    0x07
 #define DEV_ENTRY_MODE_SHIFT   0x09
 
+#define MAX_DEV_TABLE_ENTRIES  0xffff
+
 /* constants to configure the command buffer */
 #define CMD_BUFFER_SIZE    8192
 #define CMD_BUFFER_UNINITIALIZED 1
@@ -255,7 +259,7 @@
 #define PAGE_SIZE_ALIGN(address, pagesize) \
                ((address) & ~((pagesize) - 1))
 /*
- * Creates an IOMMU PTE for an address an a given pagesize
+ * Creates an IOMMU PTE for an address and a given pagesize
  * The PTE has no permission bits set
  * Pagesize is expected to be a power-of-two larger than 4096
  */
@@ -334,6 +338,23 @@ extern bool amd_iommu_np_cache;
 /* Only true if all IOMMUs support device IOTLBs */
 extern bool amd_iommu_iotlb_sup;
 
+#define MAX_IRQS_PER_TABLE     256
+#define IRQ_TABLE_ALIGNMENT    128
+
+struct irq_remap_table {
+       spinlock_t lock;
+       unsigned min_index;
+       u32 *table;
+};
+
+extern struct irq_remap_table **irq_lookup_table;
+
+/* Interrupt remapping feature used? */
+extern bool amd_iommu_irq_remap;
+
+/* kmem_cache to get tables with 128 byte alignement */
+extern struct kmem_cache *amd_iommu_irq_cache;
+
 /*
  * Make iterating over all IOMMUs easier
  */
@@ -404,7 +425,7 @@ struct iommu_dev_data {
        struct list_head dev_data_list;   /* For global dev_data_list */
        struct iommu_dev_data *alias_data;/* The alias dev_data */
        struct protection_domain *domain; /* Domain the device is bound to */
-       atomic_t bind;                    /* Domain attach reverent count */
+       atomic_t bind;                    /* Domain attach reference count */
        u16 devid;                        /* PCI Device ID */
        bool iommu_v2;                    /* Device can make use of IOMMUv2 */
        bool passthrough;                 /* Default for device is pt_domain */
@@ -565,6 +586,16 @@ struct amd_iommu {
        u32 stored_l2[0x83];
 };
 
+struct devid_map {
+       struct list_head list;
+       u8 id;
+       u16 devid;
+};
+
+/* Map HPET and IOAPIC ids to the devid used by the IOMMU */
+extern struct list_head ioapic_map;
+extern struct list_head hpet_map;
+
 /*
  * List with all IOMMUs in the system. This list is not locked because it is
  * only written and read at driver initialization or suspend time
@@ -678,6 +709,30 @@ static inline u16 calc_devid(u8 bus, u8 devfn)
        return (((u16)bus) << 8) | devfn;
 }
 
+static inline int get_ioapic_devid(int id)
+{
+       struct devid_map *entry;
+
+       list_for_each_entry(entry, &ioapic_map, list) {
+               if (entry->id == id)
+                       return entry->devid;
+       }
+
+       return -EINVAL;
+}
+
+static inline int get_hpet_devid(int id)
+{
+       struct devid_map *entry;
+
+       list_for_each_entry(entry, &hpet_map, list) {
+               if (entry->id == id)
+                       return entry->devid;
+       }
+
+       return -EINVAL;
+}
+
 #ifdef CONFIG_AMD_IOMMU_STATS
 
 struct __iommu_counter {