iommu/amd: Add slab-cache for irq remapping tables

[~andy/linux] / drivers / iommu / amd_iommu_types.h

diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h
index d0dab865a8b8bc8c6f0cd6603f6b4c9e2110e200..953cea80daa78276d0b4dd1a82814d9c004ecb43 100644 (file)
--- a/drivers/iommu/amd_iommu_types.h
+++ b/drivers/iommu/amd_iommu_types.h
@@ -334,6 +334,15 @@ extern bool amd_iommu_np_cache;
 /* Only true if all IOMMUs support device IOTLBs */
 extern bool amd_iommu_iotlb_sup;
 
+#define MAX_IRQS_PER_TABLE     256
+#define IRQ_TABLE_ALIGNMENT    128
+
+/* Interrupt remapping feature used? */
+extern bool amd_iommu_irq_remap;
+
+/* kmem_cache to get tables with 128 byte alignement */
+extern struct kmem_cache *amd_iommu_irq_cache;
+
 /*
  * Make iterating over all IOMMUs easier
  */
@@ -565,6 +574,16 @@ struct amd_iommu {
        u32 stored_l2[0x83];
 };
 
+struct devid_map {
+       struct list_head list;
+       u8 id;
+       u16 devid;
+};
+
+/* Map HPET and IOAPIC ids to the devid used by the IOMMU */
+extern struct list_head ioapic_map;
+extern struct list_head hpet_map;
+
 /*
  * List with all IOMMUs in the system. This list is not locked because it is
  * only written and read at driver initialization or suspend time
@@ -678,6 +697,30 @@ static inline u16 calc_devid(u8 bus, u8 devfn)
        return (((u16)bus) << 8) | devfn;
 }
 
+static inline int get_ioapic_devid(int id)
+{
+       struct devid_map *entry;
+
+       list_for_each_entry(entry, &ioapic_map, list) {
+               if (entry->id == id)
+                       return entry->devid;
+       }
+
+       return -EINVAL;
+}
+
+static inline int get_hpet_devid(int id)
+{
+       struct devid_map *entry;
+
+       list_for_each_entry(entry, &hpet_map, list) {
+               if (entry->id == id)
+                       return entry->devid;
+       }
+
+       return -EINVAL;
+}
+
 #ifdef CONFIG_AMD_IOMMU_STATS
 
 struct __iommu_counter {