ARM: S3C24XX: Update missed gpio calls to use gpiolib

[~andy/linux] / drivers / ide / ide-timings.c

diff --git a/drivers/ide/ide-timings.c b/drivers/ide/ide-timings.c
index c6053ab2b6c67b69bf946baa12072933dd3d9ce2..0e05f75934c98c7fccb73286d6270a1011c215c6 100644 (file)
--- a/drivers/ide/ide-timings.c
+++ b/drivers/ide/ide-timings.c
@@ -166,7 +166,7 @@ int ide_timing_compute(ide_drive_t *drive, u8 speed,
        if (id[ATA_ID_FIELD_VALID] & 2) {       /* EIDE drive */
                memset(&p, 0, sizeof(p));
 
-               if (speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
+               if (speed >= XFER_PIO_0 && speed < XFER_SW_DMA_0) {
                        if (speed <= XFER_PIO_2)
                                p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO];
                        else if ((speed <= XFER_PIO_4) ||
@@ -186,11 +186,10 @@ int ide_timing_compute(ide_drive_t *drive, u8 speed,
        /*
         * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
         * S.M.A.R.T and some other commands. We have to ensure that the
-        * DMA cycle timing is slower/equal than the fastest PIO timing.
+        * DMA cycle timing is slower/equal than the current PIO timing.
         */
        if (speed >= XFER_SW_DMA_0) {
-               u8 pio = ide_get_best_pio_mode(drive, 255, 5);
-               ide_timing_compute(drive, XFER_PIO_0 + pio, &p, T, UT);
+               ide_timing_compute(drive, drive->pio_mode, &p, T, UT);
                ide_timing_merge(&p, t, t, IDE_TIMING_ALL);
        }